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    Row hammer mitigation using a victim cache
    121.
    发明授权
    Row hammer mitigation using a victim cache 有权

    公开(公告)号：US12242388B2

    公开(公告)日：2025-03-04

    申请号：US17945702

    申请日：2022-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Ameen D. Akel ,  Shivam Swami

    IPC: G06F12/12 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/122

    Abstract: Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

    MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
    122.
    发明申请
    MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20250036316A1

    公开(公告)日：2025-01-30

    申请号：US18771865

    申请日：2024-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Chun-Yi Liu ,  Ameen D. Akel

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for management command techniques for stacked memory architectures are described. For example, a system may be configured to support management command signaling between a controller (e.g., of a host system) and interface circuitry (e.g., of a memory system) of a first semiconductor die that is configured for accessing one or more memory arrays (e.g., of the memory system) of one or more second semiconductor dies. The interface circuitry may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate a request to the controller to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation.

    MEMORY CHIP HAVING AN INTEGRATED DATA MOVER
    123.
    发明申请
    MEMORY CHIP HAVING AN INTEGRATED DATA MOVER 有权

    公开(公告)号：US20240427708A1

    公开(公告)日：2024-12-26

    申请号：US18828657

    申请日：2024-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean Stephen Eilert ,  Justin M. Eno ,  Ameen D. Akel

    IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

    Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

    ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT
    126.
    发明公开
    ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT 审中-公开

    公开(公告)号：US20240233870A9

    公开(公告)日：2024-07-11

    申请号：US18049506

    申请日：2022-10-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

    IPC: G16B30/10 ,  G16B50/00

    CPC classification number: G16B30/10 ,  G16B50/00

    Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

    In-memory associative processing for vectors
    129.
    发明授权
    In-memory associative processing for vectors 有权

    公开(公告)号：US12001708B2

    公开(公告)日：2024-06-04

    申请号：US17647944

    申请日：2022-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

    Memory device with on-die cache
    130.
    发明授权
    Memory device with on-die cache 有权

    公开(公告)号：US11947453B2

    公开(公告)日：2024-04-02

    申请号：US17100453

    申请日：2020-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

    IPC: G06F12/0802 ,  G06F3/06

    CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/22 ,  G06F2212/221

    Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

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