公开(公告)号：US20240170057A1

公开(公告)日：2024-05-23

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US11977480B2

公开(公告)日：2024-05-07

申请号：US17854797

申请日：2022-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0614 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0253 ,  G06F2212/7211

Abstract: A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

公开(公告)号：US11923001B2

公开(公告)日：2024-03-05

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/34 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US20240071553A1

公开(公告)日：2024-02-29

申请号：US17894528

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

公开(公告)号：US20240061583A1

公开(公告)日：2024-02-22

申请号：US17889836

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Ching-Huang Lu ,  Murong Lang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0629

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

公开(公告)号：US11881284B2

公开(公告)日：2024-01-23

申请号：US17546431

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

CPC classification number: G11C7/1063

Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

公开(公告)号：US20230420066A1

公开(公告)日：2023-12-28

申请号：US18242884

申请日：2023-09-06

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

IPC: G11C29/50 ,  G06F3/06

CPC classification number: G11C29/50004 ,  G06F3/0679

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.

公开(公告)号：US11735284B2

公开(公告)日：2023-08-22

申请号：US17961193

申请日：2022-10-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G11C29/10

CPC classification number: G11C29/10

Abstract: A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values for seasoning operations by modifying a first trim value of the baseline trim values; causing each memory sub-system of a plurality of memory sub-systems to perform seasoning operations using the first modified set of trim values; responsive to determining that a memory sub-system of the plurality of memory sub-system failed to satisfy a predetermined criterion, determining whether the memory sub-system is extrinsically defective; responsive to determining that the memory sub-system is extrinsically defective, removing the extrinsically defective memory sub-system from the set of memory sub-systems; and generating a second modified set of trim values for seasoning operations.

公开(公告)号：US11698731B2

公开(公告)日：2023-07-11

申请号：US17396299

申请日：2021-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: Responsive to a power-on of a memory device, an elapsed power-off time is identified based on a difference between a time at which the power-on occurred and a time at which a previous power-off of the memory device occurred. Responsive to a determination that the elapsed power-off time satisfies the elapsed time threshold criterion, a request to perform a first write operation on a memory unit of the memory device since power on is received, a performance parameter associated with the memory unit of the memory device is changed to a first parameter value that corresponds to a reduced performance level, and the write operation is performed on the memory unit of the memory device in accordance with the first parameter value that corresponds to the reduced performance level. Responsive to completion of the write operation, the performance parameter is changed to a value that corresponds to a normal performance level.

公开(公告)号：US20230207003A1

公开(公告)日：2023-06-29

申请号：US17561340

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C11/5678

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zeroto-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.