公开(公告)号：US12136456B2

公开(公告)日：2024-11-05

申请号：US17948582

申请日：2022-09-20

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

IPC: G11C29/00 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/56

Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the array of memory cells using a reference voltage and determine an amount by which to adjust the reference voltage used to sense the codeword based on an estimated weight of the original codeword, a mean of threshold voltage values of each memory cell of the sensed codeword, and a total quantity of memory cells of the sensed codeword. The circuitry can further be configured to adjust the reference voltage used to sense the codeword by the determined amount.

公开(公告)号：US20240345965A1

公开(公告)日：2024-10-17

申请号：US18755382

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Federica Cresci

IPC: G06F12/14 ,  G06F12/02 ,  G06F17/16

CPC classification number: G06F12/1441 ,  G06F12/0238 ,  G06F12/1483 ,  G06F17/16

Abstract: Methods, systems, and devices for address scrambling by linear maps in Galois fields are described. For instance, a device may determine a bijective matrix based on a power up condition. In some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. In some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. The device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.

公开(公告)号：US12072766B2

公开(公告)日：2024-08-27

申请号：US17959412

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Joseph M. McCrate

IPC: G06F11/10

CPC classification number: G06F11/1096

Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.

公开(公告)号：US12027212B2

公开(公告)日：2024-07-02

申请号：US17948556

申请日：2022-09-20

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/12 ,  G11C16/3404

Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.

公开(公告)号：US11949428B2

公开(公告)日：2024-04-02

申请号：US17843171

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Di Hsien Ngu

IPC: H03M13/09 ,  H03K19/173 ,  H03M13/11

CPC classification number: H03M13/098 ,  H03K19/1737 ,  H03M13/1171 ,  H03M13/1174

Abstract: A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

公开(公告)号：US20240103741A1

公开(公告)日：2024-03-28

申请号：US17952614

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

公开(公告)号：US11942175B2

公开(公告)日：2024-03-26

申请号：US17874897

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Stephen S. Pawlowski

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/10 ,  G11C29/44 ,  H03M13/27

CPC classification number: G11C29/42 ,  G11C7/1042 ,  G11C29/10 ,  G11C29/44 ,  H03M13/27

Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

公开(公告)号：US20240094991A1

公开(公告)日：2024-03-21

申请号：US17945260

申请日：2022-09-15

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F7/58 ,  G11C11/4076 ,  H03K3/84 ,  H03K19/21

CPC classification number: G06F7/582 ,  G11C11/4076 ,  H03K3/84 ,  H03K19/21

Abstract: Methods, systems, and devices related to generating, by a pseudorandom binary sequence (PRBS) generator of a memory module, a PRBS comprising a first plurality of bits corresponding to a plurality of cycles of a clock signal of the memory module subsequent to a current cycle of the clock signal. Generation of the PRBS can be based on an intermediate PRBS comprising a second plurality of bits corresponding to the current cycle of the clock signal. During each respective cycle of the clock signal, a respective subset of the PRBS can be communicated from the PRBS generator to a memory device of the memory module. Each respective subset of the PRBS comprises a quantity of bits based on a frequency of a data strobe signal of the memory device relative to a frequency of the clock signal.

公开(公告)号：US20240071511A1

公开(公告)日：2024-02-29

申请号：US17948556

申请日：2022-09-20

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/12 ,  G11C16/3404

Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.

公开(公告)号：US20240061792A1

公开(公告)日：2024-02-22

申请号：US18235289

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Marco Sforzin ,  Danilo Caraccio ,  Niccolò Izzo ,  Graziano Mirichigni ,  Massimiliano Patriarca

IPC: G06F12/14 ,  G06F12/0804

CPC classification number: G06F12/1458 ,  G06F12/0804

Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.