公开(公告)号：US20220077168A1

公开(公告)日：2022-03-10

申请号：US17012741

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20220037358A1

公开(公告)日：2022-02-03

申请号：US17502501

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  G11C16/08 ,  H01L27/11565

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US11158718B2

公开(公告)日：2021-10-26

申请号：US16383862

申请日：2019-04-15

Applicant: Micron Technology, inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US10957775B2

公开(公告)日：2021-03-23

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/49

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US10748921B2

公开(公告)日：2020-08-18

申请号：US16171160

申请日：2018-10-25

Applicant: Micron Technology, Inc.

Inventor： Liu Liu ,  David Daycock ,  Rithu K. Bhonsle ,  Giovanni Mazzone ,  Narula Bilik ,  Jordan D. Greenlee ,  Minsoo Lee ,  Benben Li

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/32 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

公开(公告)号：US10559579B2

公开(公告)日：2020-02-11

申请号：US16443491

申请日：2019-06-17

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/285 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US10424596B2

公开(公告)日：2019-09-24

申请号：US15852955

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/788

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US20190088671A1

公开(公告)日：2019-03-21

申请号：US15710432

申请日：2017-09-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

公开(公告)号：US12300616B2

公开(公告)日：2025-05-13

申请号：US18214911

申请日：2023-06-27

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.