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    Reduced transport energy in a memory system
    121.
    发明授权
    Reduced transport energy in a memory system 有权

    公开(公告)号：US10199089B2

    公开(公告)日：2019-02-05

    申请号：US15876539

    申请日：2018-01-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

    IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4097

    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

    Multi-Mode Memory Module and Memory Component
    122.
    发明申请
    Multi-Mode Memory Module and Memory Component 审中-公开

    公开(公告)号：US20180137067A1

    公开(公告)日：2018-05-17

    申请号：US15808595

    申请日：2017-11-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

    IPC: G06F13/16 ,  G06F13/28

    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

    Multiple memory rank system and selection method thereof
    124.
    发明授权
    Multiple memory rank system and selection method thereof 有权

    公开(公告)号：US09851900B2

    公开(公告)日：2017-12-26

    申请号：US15629173

    申请日：2017-06-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F3/06 ,  G11C8/12 ,  G06F12/06

    CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

    Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

    Remapping memory cells based on future endurance measurements
    127.
    发明授权
    Remapping memory cells based on future endurance measurements 有权
    基于未来的耐久性测量重新映射存储单元

    公开(公告)号：US09442838B2

    公开(公告)日：2016-09-13

    申请号：US14058081

    申请日：2013-10-18

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  John Eric Linstadt ,  J. James Tringali ,  Hongzhong Zheng ,  Brent Steven Haukness

    IPC: G11C13/00 ,  G06F12/02 ,  G11C29/50 ,  G11C29/04

    CPC classification number: G06F12/0238 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2029/0409 ,  G11C2213/72 ,  G11C2213/79

    Abstract: A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.

    Abstract translation: 提出了一种操作包括存储器单元组的存储器件的方法。 这些组包括第一组记忆单元。 组中的每一个具有相应的物理地址，并且最初与相应的逻辑地址相关联。 该设备还包括具有物理地址但不是最初与逻辑地址相关联的附加组的存储器单元。 在该方法中，识别第一组存储器单元和附加的存储单元组之间的未来耐久性的差异。 当第一组和附加组之间的未来耐久性的差异超过预定阈值差时，第一组和最初与第一组相关联的逻辑地址之间的关联结束，并且附加组与逻辑地址相关联， 最初与第一组有关。

    MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE
    128.
    发明申请
    MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE 有权
    存储器控制器和使用错误检测校正码的数据总线反相方法

    公开(公告)号：US20160173128A1

    公开(公告)日：2016-06-16

    申请号：US14941564

    申请日：2015-11-14

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: H03M13/05 ,  G06F3/06 ,  H03M13/00 ,  G06F13/16

    CPC classification number: H03M13/05 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F13/1668 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/19

    Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

    Abstract translation: 公开了存储器控制器，设备和相关方法。 在一个实施例中，存储器控制器包括用于将写入数据发送到存储器件的写入电路，写入电路包括写入错误检测校正（EDC）编码器，以产生与写入数据相关联的第一错误信息。 数据总线反相（DBI）电路基于阈值条件有条件地反转与每个写入数据字相关联的数据位。 读取电路从存储器件接收读取数据。 读取电路包括读取EDC编码器以产生与接收到的读取数据相关联的第二错误信息。 逻辑评估第一和第二错误信息，并且基于解码有条件地反转至少一部分读取数据。

    Hierarchical bank group timing
    129.
    发明授权
    Hierarchical bank group timing 有权

    公开(公告)号：US12230355B2

    公开(公告)日：2025-02-18

    申请号：US17634370

    申请日：2020-08-13

    Applicant: Rambus Inc.

    Inventor： John Eric Linstadt ,  Liji Gopalakrishnan ,  Thomas Vogelsang

    IPC: G11C7/10 ,  G11C7/22

    Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

    Memory module with dedicated repair devices
    130.
    发明授权
    Memory module with dedicated repair devices 有权

    公开(公告)号：US12222829B2

    公开(公告)日：2025-02-11

    申请号：US18373219

    申请日：2023-09-26

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

    IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

    Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

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