公开(公告)号：US20170031094A1

公开(公告)日：2017-02-02

申请号：US15186610

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Shinichi WATANUKI

IPC: G02B6/122 ,  G02B6/136 ,  G02F1/025 ,  G02B6/124

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B6/34 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12107 ,  G02F1/025

Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.

Abstract translation: 包括光波导和p型半导体部分的半导体器件被配置如下。 光波导包括：形成在绝缘层上的第一半导体层; 形成在所述第一半导体层上的绝缘层; 以及形成在所述绝缘层上的第二半导体层。 p型半导体部分包括第一半导体层。 p型半导体部的膜厚小于光波导的膜厚。 通过在第一半导体层和第二半导体层之间形成绝缘层，便于光波导和p型半导体部分的膜厚的控制。 具体地说，当在形成p型半导体部分的步骤中通过蚀刻除去不必要的第二半导体层时，作为下层的绝缘层用作蚀刻停止层，p型半导体部分的膜厚可以 容易调整。

公开(公告)号：US20160334573A1

公开(公告)日：2016-11-17

申请号：US15152117

申请日：2016-05-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki KUNISHIMA ,  Yasutaka NAKASHIBA ,  Masaru WAKABAYASHI ,  Shinichi WATANUKI

IPC: G02B6/122 ,  G02B6/28 ,  H01L23/522 ,  G02F1/025 ,  H01L23/528 ,  H01L23/532

CPC classification number: G02F1/025 ,  G02B6/125 ,  G02B6/132 ,  G02B6/2852 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02B2006/12147 ,  G02F2201/08 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2224/05

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

Abstract translation: 在具有第一反射率的光学定向耦合器和第一层布线之间形成具有比第一反射率低的第二反射率（50％或更低）的低反射率膜。 因此，即使当第一层布线形成在光学定向耦合器上方时，由第一层布线反射的光对通过光学定向耦合器的第一光波导和第二光波导传播的光信号的影响可以 减少 因此，第一层布线可以布置在光学定向耦合器的上方，并且第一层布线的布局的限制被放宽。

公开(公告)号：US20150357404A1

公开(公告)日：2015-12-10

申请号：US14715641

申请日：2015-05-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki SATO ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L23/528 ,  H01L28/20 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region. A field oxide film surrounds the first region in a plan view. A metal interconnect situated over a field oxide film. The metal interconnect formed of a metal having an electric resistivity at 25° C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Further, the metal interconnect is repeatedly provided spirally in a direction along the edges of the first region. Further, the metal interconnect is electrically connected at the innermost circumference with the drain region, and is connected at the outermost circumference to the source region or a ground potential.

Abstract translation: 在超过漏极区域和源极区域的区域中抑制电场的浓度的半导体器件。 漏极区域形成在第一区域中，源区域形成在第二区域中。 在平面图中，场氧化膜围绕第一区域。 位于场氧化膜上方的金属互连。 在25℃下的电阻率为40μΩ·cm〜0.8cm以上且200μΩ·cm以上的金属构成的金属配线。 此外，金属互连在沿着第一区域的边缘的方向上螺旋地重复设置。 此外，金属互连件在最内周与漏区电连接，并且在最外周连接到源极区域或接地电位。

公开(公告)号：US20150060948A1

公开(公告)日：2015-03-05

申请号：US14472665

申请日：2014-08-29

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yutaka AKIYAMA ,  Yasutaka NAKASHIBA

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/201 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/404 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member.

Abstract translation: 场板引起过大的栅极电容干扰高速晶体管切换。 为了抑制过剩的栅极电容，孔包括位于漏极侧的第一侧壁和位于源极侧的第二侧壁。 栅电极同时包括从俯视图看的与漏电极相对的第一侧表面。 从平面看，栅电极的第一侧表面位于第一侧壁和第二侧壁的内侧。 此外，第一场板的一部分嵌入在第一侧面和第一侧壁之间。 栅电极和第一场板由第一绝缘构件电绝缘。

公开(公告)号：US20150035116A1

公开(公告)日：2015-02-05

申请号：US14518024

申请日：2014-10-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L25/0655 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/528 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract translation: 在半导体器件中，第一半导体芯片包括第一电路和第一电感器，第二半导体芯片包括第二电路和芯片侧连接端子。 互连基板被放置在第一半导体芯片和第二半导体芯片上。 互连基板包括第二电感器和基板侧连接端子。 第二电感器位于第一电感器的上方。 芯片侧连接端子和两个基板侧连接端子通过第一焊球连接。

公开(公告)号：US20140078709A1

公开(公告)日：2014-03-20

申请号：US14012324

申请日：2013-08-28

Applicant: Renesas Electronics Corporation

Inventor： Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Takatsugu NEMOTO

IPC: H01L23/58

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor.An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US20130241017A1

公开(公告)日：2013-09-19

申请号：US13886693

申请日：2013-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA

IPC: H01L31/02

CPC classification number: H01L31/02 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14678

Abstract: A solid-state image pickup device 1 is back surface incident type and includes a semiconductor substrate 10, a semiconductor layer 20 and a light receiving unit 30. The solid-state image pickup device 1 photoelectrically converts light incident on the back surface S2 of the semiconductor substrate 10 into signal electrical charges to image an object. The semiconductor substrate 10 has a resistivity ρ1. A semiconductor layer 20 is provided on the surface S1 of the semiconductor substrate 10. The semiconductor layer 20 has a resistivity ρ2. Where, ρ2>ρ1. A light receiving unit 30 is formed in the semiconductor layer 20. The light receiving unit 30 receives signal charges produced by the photoelectric conversion.

Abstract translation: 固态摄像装置1是背面入射型，并且包括半导体衬底10，半导体层20和光接收单元30.固态摄像装置1对入射在背面S2上的光进行光电转换 将半导体衬底10转换成用于对物体成像的信号电荷。 半导体衬底10具有电阻率rho1。 半导体层20设置在半导体衬底10的表面S1上。半导体层20具有电阻率rho2。 哪里，rho2> rho1。 光接收单元30形成在半导体层20中。光接收单元30接收由光电转换产生的信号电荷。

公开(公告)号：US20130147010A1

公开(公告)日：2013-06-13

申请号：US13760812

申请日：2013-02-06

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA

IPC: H01L23/48

CPC classification number: H01L23/585 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.

Abstract translation: 半导体器件（1）包括布线（10）和虚设导体图案（20）。 布线（10）是流过5GHz以上的电流的布线。 在布线（10）附近，形成虚设导体图案（20）。 每个虚设导体图案（20）的平面形状等同于内角大于180°的形状。