公开(公告)号：US20160104644A1

公开(公告)日：2016-04-14

申请号：US14512700

申请日：2014-10-13

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract translation: 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

公开(公告)号：US20160013096A1

公开(公告)日：2016-01-14

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09206526B2

公开(公告)日：2015-12-08

申请号：US13901298

申请日：2013-05-23

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: G02B6/032 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/13 ,  G02B6/136 ,  G02B6/122 ,  G02B6/12

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract translation: 在非牺牲半导体材料衬底层的顶部上形成牺牲半导体材料条。 外延生长非牺牲半导体材料的保形层以覆盖基底层和牺牲半导体材料条。 执行蚀刻以选择性地去除牺牲半导体材料条并留下被保形层和基底层包围的中空通道。 使用退火，共形层和基底层被回流以产生包括中空通道的光波导结构。

公开(公告)号：US20150325487A1

公开(公告)日：2015-11-12

申请号：US14802407

申请日：2015-07-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US09171757B2

公开(公告)日：2015-10-27

申请号：US14096515

申请日：2013-12-04

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract translation: 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

公开(公告)号：US09082852B1

公开(公告)日：2015-07-14

申请号：US14560472

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-Chen Yeh

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Abstract translation: FinFET包括支撑第一晶体管和第二晶体管的半导体鳍片。 第一晶体管栅极电极延伸在鳍片的第一沟道区域上，第二晶体管栅电极在鳍片的第二沟道区域上延伸。 翅片顶部的外延生长材料在第一晶体管栅电极的第一侧上形成升高的源极区，在第一晶体管栅电极的第二侧和第二晶体管栅电极的第一侧之间的中间区域，以及 在所述第二晶体管栅电极的第二侧上的升高的漏极区。 第一和第二晶体管栅极彼此短路，其中第一晶体管被配置为具有第一阈值电压，并且第二晶体管被配置为具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09018057B1

公开(公告)日：2015-04-28

申请号：US14048263

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract translation: 一种用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括提供包括具有第一和第二横向相邻应力半导体部分的应力半导体层的受应力的绝缘体上硅（sSOI）晶片。 第一应力半导体部分限定第一有源区。 第二应力半导体部分被未受应力的半导体部分代替。 未受应力的半导体部分包括第一半导体材料。 该方法还包括将第二半导体材料驱动到限定第二有源区的无应力半导体部分的第一半导体材料中。

公开(公告)号：US08999815B2

公开(公告)日：2015-04-07

申请号：US14478347

申请日：2014-09-05

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Junli Wang

IPC: H01L21/44 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/82 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract translation: 描述了一种用于制造具有使翅片与基板绝缘的绝缘层的finFET器件的方法。 绝缘层可以防止否则将流过衬底中的体半导体材料的漏电流。 该结构可以由体半导体衬底开始制造，而不需要绝缘体上半导体衬底。 鳍结构可以通过外延生长形成，这可以提高器件中翅片高度的均匀性。

公开(公告)号：US08975168B2

公开(公告)日：2015-03-10

申请号：US13903630

申请日：2013-05-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/00 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 制造硅 - 锗半导体材料的外延生长以覆盖底部。 然后将锗从外延生长的硅 - 锗材料驱动到底部，以将底部部​​分转化为硅 - 锗。 执行进一步的硅 - 锗生长以在与第一区域中的硅区域相邻的第二区域中限定硅 - 锗区域。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20140353718A1

公开(公告)日：2014-12-04

申请号：US13907460

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

Abstract translation: 一种具有沟道外延硅的改进的晶体管及其制造方法。 一方面，一种用于制造晶体管的方法包括：在外延硅区域上形成栅极叠层结构，外延硅区域的宽度尺寸近似于栅极堆叠结构的宽度尺寸; 将所述外延硅区域封装在所述栅极堆叠结构之下，并且在所述栅极堆叠结构和所述外延硅区域的两侧上形成牺牲间隔物; 形成晶体管的沟道，其宽度尺寸近似于形成在晶体管的沟道上的外延硅区域和栅极堆叠结构，外延硅区域和栅极堆叠结构; 去除牺牲隔离物; 并且从硅衬底生长隆起的外延源和漏极，其中凸起的外延源和漏极的一部分与外延硅区接触。