公开(公告)号：US20240055436A1

公开(公告)日：2024-02-15

申请号：US18231382

申请日：2023-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  G02F1/1345 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L27/1225 ,  G02F1/13454 ,  H01L29/7869 ,  H01L29/66969 ,  H01L29/045 ,  H01L29/66742 ,  H01L27/124 ,  H01L27/1285 ,  G02F1/1368

Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

公开(公告)号：US20230169998A1

公开(公告)日：2023-06-01

申请号：US18101140

申请日：2023-01-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G11C5/10 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00 ,  G11C7/18

CPC classification number: G11C5/10 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50 ,  G11C7/18 ,  H01L27/1225 ,  H10B12/482

Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

公开(公告)号：US20230064813A1

公开(公告)日：2023-03-02

申请号：US17980693

申请日：2022-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/3291 ,  H01L29/786 ,  H03K19/003 ,  H03K19/096 ,  G11C19/28 ,  H03K17/16 ,  G09G3/36 ,  G11C19/18

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20220208139A1

公开(公告)日：2022-06-30

申请号：US17693602

申请日：2022-03-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G09G5/00 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12

Abstract: The liquid crystal display device includes a pixel portion including a plurality of pixels to which image signals are supplied; a driver circuit including a signal line driver circuit which selectively controls a signal line and a gate line driver circuit which selectively controls a gate line; a memory circuit which stores the image signals; a comparison circuit which compares the image signals stored in the memory circuit in the pixels and detects a difference; and a display control circuit which controls the driver circuit and reads the image signal in accordance with the difference. The display control circuit supplies the image signal only to the pixel where the difference is detected. The pixel includes a thin film transistor including a semiconductor layer including an oxide semiconductor.

公开(公告)号：US20220173129A1

公开(公告)日：2022-06-02

申请号：US17539249

申请日：2021-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  G02F1/1345 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04

Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

公开(公告)号：US20220165758A1

公开(公告)日：2022-05-26

申请号：US17666938

申请日：2022-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L27/088 ,  H01L29/04

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

公开(公告)号：US20220133150A1

公开(公告)日：2022-05-05

申请号：US17580772

申请日：2022-01-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: A61B5/00 ,  H05K1/11 ,  A61B5/07 ,  G16H40/67 ,  H05K7/00 ,  H01L23/60 ,  H01L23/66 ,  H01L27/13 ,  H04B1/16 ,  H04B13/00 ,  G16H40/63

Abstract: A wireless sensor device capable of constant operation without replacement of batteries. The wireless sensor device is equipped with a rechargeable battery and the battery is recharged wirelessly. Radio waves received at an antenna circuit are converted into electrical energy and stored in the battery. A sensor circuit operates with the electrical energy stored in the battery, and acquires information. Then, a signal containing the information acquired is converted into radio waves at the antenna circuit, whereby the information can be read out wirelessly.

公开(公告)号：US20220059531A1

公开(公告)日：2022-02-24

申请号：US17520977

申请日：2021-11-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/088 ,  G11C11/405 ,  G11C11/404 ,  G11C16/02 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/105

Abstract: It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

公开(公告)号：US20210328580A1

公开(公告)日：2021-10-21

申请号：US17359940

申请日：2021-06-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: H03K3/012 ,  G11C8/04 ,  H03K3/037 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/786 ,  H01L27/12 ,  H03K19/00 ,  G11C5/14 ,  H01L27/06 ,  H01L29/04

Abstract: Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

公开(公告)号：US20210296371A1

公开(公告)日：2021-09-23

申请号：US17340165

申请日：2021-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/3291 ,  H01L29/786 ,  H03K19/003 ,  H03K19/096 ,  G11C19/28 ,  H03K17/16 ,  G09G3/36 ,  G11C19/18

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.