公开(公告)号：US10593775B2

公开(公告)日：2020-03-17

申请号：US16228872

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia Yeo ,  Sung-Li Wang ,  Chi On Chui ,  Jyh-Cherng Sheu ,  Hung-Li Chiang ,  I-Sheng Chen

IPC: H01L29/45 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20200035562A1

公开(公告)日：2020-01-30

申请号：US16595007

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US10269800B2

公开(公告)日：2019-04-23

申请号：US15605983

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.

公开(公告)号：US10134640B1

公开(公告)日：2018-11-20

申请号：US15652628

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Chao-Ching Cheng ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.

公开(公告)号：US10008418B2

公开(公告)日：2018-06-26

申请号：US15282981

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chia-Ping Lo ,  Liang-Gi Yao ,  Weng Chang ,  Yee-Chia Yeo ,  Ziwei Fang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/324 ,  H01L21/02 ,  H01L21/268

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

公开(公告)号：US09472669B1

公开(公告)日：2016-10-18

申请号：US14846414

申请日：2015-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Cheng-Yi Peng ,  Jyh-Cherng Sheu ,  Yee-Chia Yeo

IPC: H01L21/336 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating layer. A gate structure is formed over the first and second fin structures, each of which has source/drain regions, having a first width, outside of the gate structure. Portions of sidewalls of the source/drain regions are removed to form trimmed source/drain regions, each of which has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions such that the strain material formed on the first fin structure is separated from that on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material such that the contact layer wraps around the strain material.

Abstract translation: 在制造Fin FET的方法中，形成第一和第二鳍结构。 第一和第二翅片结构从隔离绝缘层突出。 栅极结构形成在第一鳍片结构和第二鳍片结构之上，每个栅极结构具有在栅极结构外部具有第一宽度的源极/漏极区域。 去除源极/漏极区域的侧壁的部分以形成修整的源极/漏极区域，其中每个具有小于第一宽度的第二宽度。 在修整的源极/漏极区域上形成应变材料，使得形成在第一鳍状结构上的应变材料与第二鳍状结构上的应变材料分离。 在栅极结构和源极/漏极区之间用应变材料形成层间电介质层。 在应变材料上形成接触层，使得接触层缠绕在应变材料周围。

公开(公告)号：US12300496B2

公开(公告)日：2025-05-13

申请号：US18359735

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H10D64/62

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US12278146B2

公开(公告)日：2025-04-15

申请号：US18064764

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Chien-Wei Lee ,  Chien-Hung Chen ,  Wen-Chu Hsiao ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

公开(公告)号：US20250098206A1

公开(公告)日：2025-03-20

申请号：US18968754

申请日：2024-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Yi-Syuan Siao ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

公开(公告)号：US12255255B2

公开(公告)日：2025-03-18

申请号：US17815020

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092

Abstract: A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.