公开(公告)号：US20200373485A1

公开(公告)日：2020-11-26

申请号：US16991039

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L45/00 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US20200294926A1

公开(公告)日：2020-09-17

申请号：US16891076

申请日：2020-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22 ,  H01L23/498 ,  H01L21/683

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

公开(公告)号：US10770655B2

公开(公告)日：2020-09-08

申请号：US16542284

申请日：2019-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L29/40 ,  H01L21/44 ,  H01L45/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US10707173B2

公开(公告)日：2020-07-07

申请号：US16578403

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22 ,  H01L23/367 ,  H01L23/498 ,  H01L21/683 ,  H01Q1/24

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

公开(公告)号：US20200176384A1

公开(公告)日：2020-06-04

申请号：US16655260

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.

公开(公告)号：US20200176357A1

公开(公告)日：2020-06-04

申请号：US16655257

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee

IPC: H01L23/473 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L21/50

Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

公开(公告)号：US20200066671A1

公开(公告)日：2020-02-27

申请号：US16666708

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/42 ,  H01L21/56

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.

公开(公告)号：US10475747B2

公开(公告)日：2019-11-12

申请号：US15676958

申请日：2017-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US20190067169A1

公开(公告)日：2019-02-28

申请号：US15690283

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

公开(公告)号：US20180138056A1

公开(公告)日：2018-05-17

申请号：US15855305

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.