公开(公告)号：US20070195603A1

公开(公告)日：2007-08-23

申请号：US11359104

申请日：2006-02-22

申请人： Seiichi Aritome ,  Todd Marquart

发明人： Seiichi Aritome ,  Todd Marquart

IPC分类号： G11C11/34 ,  G11C5/14 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

摘要： A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.

摘要翻译： 耦合到用于编程的单元的所选字线被初始编程电压偏置。 与所选择的字线相邻的未选字线被偏置在初始V 。 随着存储器件上的编程/擦除周期数量增加，成功编程单元所需的编程电压逐渐减小。 V 跟踪编程电压的减小。

公开(公告)号：US20070195571A1

公开(公告)日：2007-08-23

申请号：US11360873

申请日：2006-02-23

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/005 ,  H01L27/115

摘要： Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.

摘要翻译： 提供了方法和装置。 在一个实施例中，存储器件包括通过第一多路复用器门选择性地耦合到感测器件的输入的第一位线，以及通过第二多路复用器门选择性地耦合到感测器件输入的第二位线。 第一位线形成在第一垂直层并且耦合到第一多路复用器门的第一源/漏区。 感测装置的输入形成在不同于第一垂直层的第二垂直层上，并且耦合到第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第一源极/漏极区域。 第二位线形成在第一垂直层处，并且耦合到第二多路复用器门的第二源极/漏极区域。

公开(公告)号：US20070171729A1

公开(公告)日：2007-07-26

申请号：US11340093

申请日：2006-01-26

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/344

摘要： The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then performed for an increasing sensing time period until either all of the memory cells of the block have a threshold voltage that is equal to or greater than an erased threshold voltage or a predetermined quantity of erase verify operations have been performed. The sensing time period for each subsequent verify operation is increased until a maximum sense time is reached. When the memory cells have all been erased, the erase voltage and erase time corresponding to the sensing time period at which the cells passed is used for further erase operations on the memory block.

摘要翻译： 闪存单元擦除操作在第一擦除时间的第一擦除电压下执行擦除操作。 然后对于增加的感测时间周期执行擦除验证读取操作，直到该块的所有存储单元具有等于或大于擦除的阈值电压的阈值电压或已经执行了预定量的擦除验证操作 。 每个后续验证操作的感测时间周期增加，直到达到最大感测时间。 当存储单元全部被擦除时，对应于单元通过的感测时间周期的擦除电压和擦除时间用于存储块上的进一步的擦除操作。

公开(公告)号：US07212447B2

公开(公告)日：2007-05-01

申请号：US11197641

申请日：2005-08-04

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

摘要： A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells, the voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block.

摘要翻译： 具有布置在第一和第二可寻址块中的浮置晶体管存储单元的阵列的诸如NAND闪存的闪速存储器件。 将编程电压提供给浮动栅极晶体管存储单元的控制栅极的电压源，当数据被编程在存储器中时，电压源向位于第一可寻址块中的浮动栅极晶体管存储器单元的控制栅极提供预充电电压 第二可寻址块的单元。

公开(公告)号：US07192831B2

公开(公告)日：2007-03-20

申请号：US11100492

申请日：2005-04-07

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

摘要翻译： 非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。 沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。 层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。 第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。 第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。 金属层设置在布线沟槽中，使其与第二导电材料层电接触。

公开(公告)号：US20070047315A1

公开(公告)日：2007-03-01

申请号：US11218851

申请日：2005-09-01

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/102 ,  G11C16/26

摘要： A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

摘要翻译： 用于在存储器件中设置修剪参数的方法和装置根据观察或测试的编程速度和可靠性提供分配给存储器件部分的多个修整设置。

公开(公告)号：US20050181561A1

公开(公告)日：2005-08-18

申请号：US11100492

申请日：2005-04-07

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/3205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

公开(公告)号：US06891246B2

公开(公告)日：2005-05-10

申请号：US10178263

申请日：2002-06-25

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/3205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

摘要翻译： 非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。 沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。 层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。 第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。 第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。 金属层设置在布线沟槽中，使其与第二导电材料层电接触。

公开(公告)号：US06703658B2

公开(公告)日：2004-03-09

申请号：US10429460

申请日：2003-05-05

申请人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： H01L27108

CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  Y10S257/908

摘要： In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

摘要翻译： 在非易失性半导体存储器件及其制造方法中，每个存储单元及其选择Tr具有与Vcc Tr相同的栅极绝缘膜。 此外，Vpp Tr和Vcc Tr的栅极通过使用第一多晶硅层来实现。 可以在第一多晶硅层上提供与第二多晶硅（形成控制栅极层）不同的诸如硅化物或金属的材料。 利用上述特征，可以通过减小的步骤制造非易失性半导体存储器件并以可靠的方式高速运行。

公开(公告)号：US06495896B1

公开(公告)日：2002-12-17

申请号：US09407401

申请日：1999-09-28

申请人： Toshitake Yaegashi ,  Seiichi Aritome ,  Yuji Takeuchi ,  Kazuhiro Shimizu

发明人： Toshitake Yaegashi ,  Seiichi Aritome ,  Yuji Takeuchi ,  Kazuhiro Shimizu

IPC分类号： H01L2900

CPC分类号： H01L27/11526 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/11531

摘要： A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p−-type well is formed, a p−-type well 15-1 formed in the substrate 1, a p−-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p−-type well 15-1, and an n-type well 12-2 which is formed below the p−-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs. Alternatively, low-voltage n-channel MOS transistors QN1, QN2 and low-voltage p-channel MOS transistors QP1, QP2 are formed in a p-type well 214 and n-type well 213 of a p−-type silicon substrate 211, respectively, and high-voltage n-channel MOS transistors QN3, QN4 are formed in the substrate 211. The p-type well 214, in which the transistors QN1, QN2 are formed, and the p-type element isolating layer 215 of the element isolating regions for the transistors QN3, QN4 are simultaneously formed by ion implantation using a resist mask by the lithography on a flat surface having no step. The p-type well 214 and the p-type element isolating layer 215 have the same depth from the substrate surface of the element regions and the same impurity density. Thus, it is possible to provide a semiconductor integrated circuit device capable of achieving good element isolation characteristics, and a method for producing the same.

摘要翻译： 半导体集成电路器件包括形成在p型硅衬底1中的n型阱8-1，形成为围绕衬底1的一部分的n型阱8-2，其中p型 形成良好的p型阱15-1，形成在衬底1中的p型阱15-1，形成在衬底1的被n型阱包围的部分中的p型阱15-2，嵌入 n型阱12-1形成在p型阱15-1的下方，n型阱12-2形成在p型阱15-2的下方，并与n型阱15-1连接。 好8-2。 因此，可以提供能够抑制光刻步骤数量增加并降低制造成本的半导体集成电路器件。或者，低电压n沟道MOS晶体管QN1，QN2和低压p沟道MOS 晶体管QP1，QP2分别形成在p型硅衬底211的p型阱214和n型阱213中，并且高压n沟道MOS晶体管QN3，QN4形成在衬底211中。 其中形成晶体管QN1，QN2的p型阱214和用于晶体管QN3，QN4的元件隔离区的p型元件隔离层215同时通过使用光刻胶的抗蚀剂掩模的离子注入形成 在没有台阶的平坦表面上。 p型阱214和p型元件隔离层215具有与元件区域的衬底表面相同的深度和相同的杂质密度。 因此，可以提供能够实现良好元件隔离特性的半导体集成电路器件及其制造方法。