公开(公告)号：US5824583A

公开(公告)日：1998-10-20

申请号：US949819

申请日：1997-10-14

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5821023A

公开(公告)日：1998-10-13

申请号：US862701

申请日：1997-05-23

申请人： Yuusaku Shibuya ,  Yasuhiro Oya ,  Haruhide Ishida ,  Susumu Yoshino ,  Hirokazu Hamano ,  Kaori Ohishi ,  Satoshi Inoue ,  Jun Igarashi ,  Chiaki Suzuki ,  Sueko Sakai

发明人： Yuusaku Shibuya ,  Yasuhiro Oya ,  Haruhide Ishida ,  Susumu Yoshino ,  Hirokazu Hamano ,  Kaori Ohishi ,  Satoshi Inoue ,  Jun Igarashi ,  Chiaki Suzuki ,  Sueko Sakai

IPC分类号： G03G9/113 ,  G03G13/08 ,  G03G15/08

CPC分类号： G03G9/113 ,  G03G9/1131

摘要： The present invention provides a long-life carrier for developing an electrostatic latent image to be used in such field of applications as electrostatic photography and electrostatic recording, a developer of an electrostatic latent image utilizing said carrier, a method for forming an image and an image forming apparatus by using said developer. By use of the foregoing qualities, a high-quality image can be obtained.

摘要翻译： 本发明提供一种用于显影静电潜像的长寿命载体，用于静电摄影和静电记录等应用领域，利用所述载体的静电潜像的显影剂，形成图像和图像的方法 通过使用所述显影剂形成装置。 通过使用上述质量，可以获得高质量的图像。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5323039A

公开(公告)日：1994-06-21

申请号：US499342

申请日：1990-06-21

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。 公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5320925A

公开(公告)日：1994-06-14

申请号：US879287

申请日：1992-05-07

申请人： Takashi Imai ,  Satoshi Inoue ,  Masanori Ichimura ,  Yutaka Sugizaki ,  Susumu Saito ,  Masaru Miura ,  Michio Take ,  Yasuo Yamamoto ,  Koji Fukushima ,  Manabu Serizawa

发明人： Takashi Imai ,  Satoshi Inoue ,  Masanori Ichimura ,  Yutaka Sugizaki ,  Susumu Saito ,  Masaru Miura ,  Michio Take ,  Yasuo Yamamoto ,  Koji Fukushima ,  Manabu Serizawa

IPC分类号： G03G9/08 ,  G03G9/097

CPC分类号： G03G9/0819 ,  G03G9/09716

摘要： An electrophotographic toner composition comprising (A) toner particles with an average particle diameter of 9 .mu.m or less comprising at least a binder resin and a colorant, and (B) an additive, wherein the additive is a fine metal oxide powder surface coated with at least one agent for imparting hydrophobic property selected from the group consisting of the following formulae (1), (2) and (3):R.sub.1 Si(X).sub.3R.sub.1 R.sub.2 Si(X).sub.2R.sub.1 R.sub.2 R.sub.3 Si(X).sub.1wherein R.sub.1 represents a substituted or unsubstituted alkyl group having a molecular weight of 113 or more, R.sub.2 and R.sub.3 each represents hydrogen, an alkyl group or an allyl group, and X represents chlorine, an alkoxy group or an acetoxy group. The toner composition causes no impaction to a carrier and no adhesion of the toner particles to a photoreceptor, and can form stable, sufficient images for a long time.

摘要翻译： 一种电子照相调色剂组合物，其包含（A）平均粒径为9μm或更小的调色剂颗粒至少包含粘合剂树脂和着色剂，和（B）添加剂，其中所述添加剂是涂覆有金属氧化物粉末表面的金属表面 至少一种赋予选自下式（1），（2）和（3）的疏水性的试剂：R1Si（X）3 R1R2Si（X）2 R1R2R3Si（X）1其中R1表示取代或 未取代的分子量为113以上的烷基，R2和R3各自表示氢，烷基或烯丙基，X表示氯，烷氧基或乙酰氧基。 调色剂组合物不会对载体造成冲击，并且不会使调色剂颗粒粘附到感光体上，并且可以长时间形成稳定的足够的图像。

公开(公告)号：US5254685A

公开(公告)日：1993-10-19

申请号：US741333

申请日：1991-08-07

申请人： Masaharu Yokomoto ,  Akira Yazaki ,  Norihiro Hayashi ,  Shunso Hatono ,  Satoshi Inoue ,  Yasuhiro Kuramoto

发明人： Masaharu Yokomoto ,  Akira Yazaki ,  Norihiro Hayashi ,  Shunso Hatono ,  Satoshi Inoue ,  Yasuhiro Kuramoto

IPC分类号： C07D471/06 ,  C07D519/00 ,  A61K31/435 ,  A61K31/50 ,  A61K31/55

CPC分类号： C07D471/06

摘要： A tricyclic compound represented by the general formula (1) and salts thereof. ##STR1## A method for producing the tricyclic compound and salts thereof, and an antimicrobial agent containing the tricyclic compound and salts thereof as an active ingredient are also disclosed.

公开(公告)号：US5248628A

公开(公告)日：1993-09-28

申请号：US896537

申请日：1992-06-09

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US5043298A

公开(公告)日：1991-08-27

申请号：US619666

申请日：1990-11-28

申请人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

发明人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L27/10808

摘要： When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.

摘要翻译： 当具有多层接触的半导体器件被制造时，栅电极被厚绝缘膜覆盖。 在至少形成接触形成区域中的栅电极被第一耐氧化绝缘膜覆盖的状态下形成多晶硅膜。 然后在至少部分多晶硅膜被第二防氧化绝缘膜覆盖的状态下形成层间绝缘膜。 使用多晶硅膜作为蚀刻阻挡层形成第一接触孔，然后将多晶硅膜氧化。 此外，在第二耐氧化绝缘膜的上表面上的层间绝缘膜中形成第二接触孔，使用作为蚀刻停止层的第二耐氧化绝缘膜的下面的多晶硅膜。 由于在第二接触形成区域中的层间绝缘体膜下方形成多晶硅膜以覆盖栅电极，所以当形成第二接触时，其作为阻挡体，从而防止栅电极的短路甚至 如果栅电极和第二触点之间没有距离。

公开(公告)号：US4939690A

公开(公告)日：1990-07-03

申请号：US290427

申请日：1988-12-27

申请人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其包括NAND单元块，每个NAND单元具有连接到相应位线的选择晶体管和存储单元晶体管的串联阵列。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据擦除模式下，通过向存储单元的控制栅极施加“H”电平电位，并将位线的“L”电平电位同时擦除所有存储单元。 在这种同时擦除之前，从存储器单元的电荷累积层去除电荷，使得存储单元的阈值被初始化。 对NAND单元块中的串联存储单元晶体管依次执行阈值初始化。

公开(公告)号：US4757771A

公开(公告)日：1988-07-19

申请号：US5177

申请日：1987-01-20

申请人： Minoru Narisoko ,  Satoshi Inoue

发明人： Minoru Narisoko ,  Satoshi Inoue

IPC分类号： F23G5/50 ,  F23G5/30 ,  F23L7/00 ,  F23G5/00 ,  F23G7/00

CPC分类号： F23G5/30 ,  F23L7/002

摘要： A method of combustion and a fluidized bed incinerator for burning and decomposing refuse such as municipal wastes are disclosed. The refuse is fluidized together with a fluidizing medium such as sand and primary air, to form a fluidized bed where the refuse is burned and decomposed. The pyrolysis gas produce by thermal decomposition of the refuse is combusted with secondary air supplied to the incinerator. By controlling the temperature inside the fluidized bed so as to be maintained in the range from 520.degree. to 650.degree. C., stable combustion is achieved, despite changes in the volume of refuse added to the fluidized bed, and the unburned pyrolysis gas and smut densities in the exhaust gas are decreased. Temperature control is achieved by spraying water onto the fluidized bed. The combustion air ratio can be reduced because the refuse can be stably combusted, and the temperature of pyrolysis gas inside the combustion chamber can be maintained at a high level.

摘要翻译： 公开了一种用于燃烧和分解垃圾的城市废物的燃烧方法和流化床焚烧炉。 垃圾与流化介质如沙子和一次空气一起流化，形成流化床，其中垃圾被燃烧和分解。 通过垃圾热分解产生的热解气体与供给焚烧炉的二次空气一起燃烧。 通过控制流化床内的温度以保持在520℃至650℃的范围内，尽管添加到流化床中的垃圾体积的变化以及未燃烧的热解气体和污迹 废气中的密度降低。 温度控制是通过将水喷洒到流化床上实现的。 由于垃圾可以稳定地燃烧，燃烧室内的热解气体的温度能够维持在高水平，所以能够降低燃烧空气比。