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321 条记录 (耗时 0.038 秒)

    Semiconductor device of hierarchical power source structure
    121.
    发明授权
    Semiconductor device of hierarchical power source structure 有权
    分层电源结构的半导体器件

    公开(公告)号：US6107700A

    公开(公告)日：2000-08-22

    申请号：US191121

    申请日：1998-11-13

    申请人： Masatoshi Ishikawa ,  Tsukasa Ooishi

    发明人： Masatoshi Ishikawa ,  Tsukasa Ooishi

    IPC分类号： H03K19/00 ,  G05F1/46 ,  G11C11/407 ,  H03K19/0944 ,  H03K19/096 ,  G05F1/10

    CPC分类号： G05F1/465 ,  Y10T307/766

    摘要： When an operation of an internal circuit is initiated, a current is supplied from an external power supply node to a sub-power source line for a predetermined period. A semiconductor device having a hierarchical power source structure is provided, which can have a voltage variation in the sub-power source line reduced and which can recover the varied voltage speedily to a predetermined voltage level in an operating state of the internal circuit.

    摘要翻译： 当启动内部电路的操作时，电流从外部电源节点提供到子电源线一段预定时间段。 提供具有分层电源结构的半导体器件，其可以使子电源线中的电压变化减小，并且可以在内部电路的操作状态下将变化的电压快速恢复到预定的电压电平。

    Semiconductor device for reducing effects of noise on an internal circuit
    123.
    发明授权
    Semiconductor device for reducing effects of noise on an internal circuit 失效
    用于减少噪声对内部电路的影响的半导体器件

    公开(公告)号：US5844262A

    公开(公告)日：1998-12-01

    申请号：US626406

    申请日：1996-04-02

    申请人： Tsukasa Ooishi

    发明人： Tsukasa Ooishi

    IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10

    CPC分类号： G11C5/147 ,  H01L27/0218 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10T307/414 ,  Y10T307/492

    摘要： Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines function as a filter. As a result, noise generated by operation of the internal circuit is absorbed in propagating to the stabilize circuit through first internal power supply line, pad, and the second internal power supply line. Therefore, effects of noise given to the stabilize circuit are small.

    摘要翻译： 根据本发明的半导体器件包括封装框架，接合线，焊盘，第一内部电源线，第二内部电源线，内部电路，稳定电路，GND封装框架，GND接合线，GND焊盘和内部GND线。 接线，焊盘，第一和第二内部电源线作为过滤器。 结果，通过内部电路的工作产生的噪声被第一内部电源线，焊盘和第二内部电源线传播到稳定电路。 因此，给予稳定电路的噪声的影响很小。

    Non-volatile semiconductor memory device and semiconductor memory device
    127.
    发明授权
    Non-volatile semiconductor memory device and semiconductor memory device 有权
    非易失性半导体存储器件和半导体存储器件

    公开(公告)号：US07672173B2

    公开(公告)日：2010-03-02

    申请号：US11902232

    申请日：2007-09-20

    申请人： Tsukasa Ooishi ,  Tomohiro Uchiyama ,  Shinya Miyazaki

    发明人： Tsukasa Ooishi ,  Tomohiro Uchiyama ,  Shinya Miyazaki

    IPC分类号： G11C7/00

    CPC分类号： G11C8/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32

    摘要： For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are reset to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

    摘要翻译： 对于每个存储器块，用于对应用的地址信号进行预编码的预解码器，用于锁存预解码器的输出信号的地址锁存电路和用于解码地址锁存电路的输出信号的解码电路，并且执行存储器单元选择操作 提供相应的存储块。 可以使锁存器预解码信号的传播延迟更小，并且可以扩大内部读取定时的余量。 此外，当选择存储单元并且根据内部数据读取的状态将内部数据输出电路复位到初始状态时，解码器和存储单元选择电路的内部状态被复位到初始状态。 因此，提供了可以减少地址偏移并实现具有足够余量的操作的非易失性半导体存储器件。

    Semiconductor device improving error correction processing rate
    128.
    发明授权
    Semiconductor device improving error correction processing rate 有权
    半导体器件提高纠错处理率

    公开(公告)号：US07552378B2

    公开(公告)日：2009-06-23

    申请号：US11148365

    申请日：2005-06-09

    申请人： Tomoya Kawagoe ,  Tsukasa Ooishi

    发明人： Tomoya Kawagoe ,  Tsukasa Ooishi

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008

    摘要： In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

    摘要翻译： 在构成ECC电路的异或电路（异或门）中，将P沟道MOS晶体管的驱动能力设定为大于N沟道MOS晶体管的驱动能力。 因此，与将驾驶性能设定为相等的情况相比，将输出节点的逻辑电平从被识别为复位状态的L电平设定为H电平的速度增加。 因此，可以减少从多级XOR门输出综合征所需的时间，以允许高速执行纠错处理。

    Nonvolatile semiconductor memory device having improved redundancy relieving rate
    129.
    发明授权
    Nonvolatile semiconductor memory device having improved redundancy relieving rate 失效
    具有改善的冗余缓解率的非易失性半导体存储器件

    公开(公告)号：US07277330B2

    公开(公告)日：2007-10-02

    申请号：US11409121

    申请日：2006-04-24

    申请人： Tsukasa Ooishi

    发明人： Tsukasa Ooishi

    IPC分类号： G11C7/10

    CPC分类号： G11C15/046 ,  G11C11/16 ,  G11C13/0004 ,  G11C15/02 ,  G11C29/816 ,  G11C29/846

    摘要： In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

    摘要翻译： 在MRAM的存储单元阵列中，将正常存储单元与保持参考值的参考存储单元进行比较，从而存储每个单元一位的数据。 两个备用存储单元整体存储一位的数据。 通过将补充值写入两个备用存储单元并将这些备用存储单元连接到读出放大器，读取一位的存储数据。 经常布置在阵列周边部分中的备用存储单元部分变得更加抵抗元件的成品尺寸的变化，并且由备用存储单元更换和释放有缺陷的存储单元的成功率增加。

    Non-volatile semiconductor memory device allowing shrinking of memory cell
    130.
    发明申请
    Non-volatile semiconductor memory device allowing shrinking of memory cell 审中-公开

    公开(公告)号：US20070158634A1

    公开(公告)日：2007-07-12

    申请号：US11716047

    申请日：2007-03-09

    申请人： Tsukasa Ooishi

    发明人： Tsukasa Ooishi

    IPC分类号： H01L29/06

    CPC分类号： G11C13/0004 ,  G11C5/02 ,  G11C7/14 ,  H01L27/24

    摘要： Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.