公开(公告)号：US5307312A

公开(公告)日：1994-04-26

申请号：US734907

申请日：1991-07-24

Applicant: Alfonso Maurelli ,  Carlo Riva

Inventor： Alfonso Maurelli ,  Carlo Riva

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L25/04 ,  H01L27/10

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883 ,  H01L27/105

Abstract: The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

Abstract translation: 该过程提供用于形成控制栅极和限定沟道区的源极和漏极的高掺杂区域的类型P的半导体衬底的区域的同时N +型注入。 在氧化物生长之后，执行多晶硅层的沉积和定义，其一个区域构成控制栅极上方的浮置栅极和沟道区域，并部分地叠加在源极和漏极区域上。

公开(公告)号：US5300451A

公开(公告)日：1994-04-05

申请号：US967553

申请日：1992-10-27

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L29/66712 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/7802 ,  H01L29/0847 ,  Y10S148/126 ,  Y10S438/98

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage by the implantation of a buried gate region in a first epitaxial layer after the formation of said epitaxial layer. These buried gate regions high dopant concentrations where the dopants have low diffusion coefficients. These low diffusive dopants permit more accurate and form defined buried gate regions than current formation techniques utilizing formation of buried gate regions implemented in the substrate where these gate regions contain highly diffusive dopants.

Abstract translation: 本发明涉及一种用于在单片半导体器件中形成埋地漏极或集电极区域的方法，其包括集成控制电路和集成在同一芯片中的垂直电流的一个或多个功率晶体管。 该过程允许通过在形成所述外延层之后在第一外延层中注入掩埋栅极区域来优化功率级的载流能力和串联漏极电阻和工作电压。 这些掩埋栅区具有高掺杂浓度，其中掺杂剂具有低扩散系数。 这些低扩散掺杂剂允许比当前形成技术更精确和形成定义的掩埋栅极区域，其利用在衬底中实现的掩埋栅极区域的形成，其中这些栅极区域包含高度漫射掺杂剂。

公开(公告)号：US5289423A

公开(公告)日：1994-02-22

申请号：US792478

申请日：1991-11-15

Applicant: Virginia Natale ,  Gianluca Petrosino ,  Flavio Scarra

Inventor： Virginia Natale ,  Gianluca Petrosino ,  Flavio Scarra

IPC: H01L27/115 ,  G11C7/00

CPC classification number: H01L27/115

Abstract: Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of the first level of metal and the relative secondary source line patterned in the second metal layer. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.

Abstract translation: FLASH-EPROM矩阵的行的单元的每个公共源区域可以被分割，并且每个段通过每个公共源区域和图案化部分之间的多个接触单独地连接到由第二层金属层图案化的次级源极线 并且通过在第一金属级的后一图案化部分和在第二金属层中图案化的相对次级源极线之间的尽可能多的互连通孔。 次级源极线从矩阵垂直于位线引出，并且可以连接到专用选择电路，从而允许由FLASH-EPROM存储器的单元的组或块组擦除。

公开(公告)号：US5283478A

公开(公告)日：1994-02-01

申请号：US811323

申请日：1991-12-20

Applicant: Franco Maloberti ,  Salvatore Portaluri ,  Guido Torelli

Inventor： Franco Maloberti ,  Salvatore Portaluri ,  Guido Torelli

IPC: G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K3/01 ,  H03K5/12

CPC classification number: H03K17/163 ,  H03K19/00361

Abstract: A fast capacitive-load driving circuit for driving output nodes on an integrated circuit. This circuit reduces noise interference caused by parasitic inductance by lowering the inductance voltage on the power supply lines during the switching process. This invention includes a voltage ramp, a voltage-to-current converter, and an output buffer having at least one pull-down transistor. A further embodiment includes an output buffer possessing a pull-down and a pull-up transistor.

Abstract translation: 一种用于驱动集成电路上的输出节点的快速电容负载驱动电路。 该电路通过在切换过程中降低电源线上的电感电压来减少由寄生电感引起的噪声干扰。 本发明包括电压斜坡，电压 - 电流转换器和具有至少一个下拉晶体管的输出缓冲器。 另一实施例包括具有下拉和上拉晶体管的输出缓冲器。

公开(公告)号：US5279982A

公开(公告)日：1994-01-18

申请号：US734503

申请日：1991-07-23

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/115

Abstract: A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells. In ROM devices, the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes. The fabrication process employs self-alignment techniques and masks with a relatively low alignment criticality.

Abstract translation: 用于EPROM或ROM型存储器的单元阵列具有分别连接在布置在直接形成在半导体衬底上的阵列的同一行上的单元的公共漏极和源极区域中的漏极和源极互连金属线，在交叉处叠加到不间断隔离 形成在半导体衬底上的用于分离属于阵列的两个相邻列的单元的栅极和栅极互连线（WORD LINES），栅极互连线（WORD LINES）连接布置在同一列上的单元的控制栅极电极，该栅极互连线平行于所述隔离带和 在交叉处叠加到所述底层源极和漏极线（BIT LINES）。 该阵列显着地比根据现有技术制成的阵列更紧凑，尽管利用具有类似光学分辨率的制造装置，同时使单元的源极和漏极接触面积最大化。 在ROM器件中，定制可以有利地在制造工艺的最后步骤期间通过相对于现有技术工艺中使用的类似漏极接触掩模具有降低的临界性的栅极接触掩模进行。 制造工艺采用自对准技术和具有较低对准关键性的掩模。

公开(公告)号：US5274282A

公开(公告)日：1993-12-28

申请号：US970609

申请日：1992-10-30

Applicant: Flavio Scarra ,  Siro M. Morganti ,  Giuseppe Meroni

Inventor： Flavio Scarra ,  Siro M. Morganti ,  Giuseppe Meroni

IPC: H03K19/177 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K19/17716

Abstract: The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).

Abstract translation: 该电路包括一个输入寄存器（RI）; 输出寄存器（RU）; 一个AND平面; 和OR平面。 AND平面具有由输入寄存器控制的垂直线（Y）和包括串联布置并由相应垂直线控制的晶体管（TA）的水平线（L）。 水平线通过常闭晶体管（TV）连接到地，并通过常开晶体管（TP）连接到电源。 这些晶体管（TV，TP）由第一时钟信号（CK1 DIFFERENCE）控制。 OR平面具有水平线（S）和垂直线（U）。 OR平面的垂直线（U）包含由OR平面的相应水平线控制的常闭晶体管（TO）。 AND平面的水平线和OR平面的水平线通过串联布置在电源和地之间的各对正常导通晶体管（TB）和常关断晶体管（TC）连接。 在每对中，常通晶体管由AND平面的水平线控制，而常闭晶体管由第二时钟信号（CK2）控制。 OR平面的水平线连接到该对之间的节点。 OR平面的垂直线通过由第三时钟信号（CK2 DIFFERENCE）控制的相应晶体管（TR）连接到电源，并且由通过晶体管（P）控制的输出寄存器 第四个时钟信号（CK3 DIFFERENCE）。

公开(公告)号：US5246871A

公开(公告)日：1993-09-21

申请号：US805048

申请日：1991-12-11

Applicant: Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

Inventor： Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

IPC: H01L21/8248 ,  H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/8248 ,  Y10S148/126

Abstract: The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.

Abstract translation: 与使用BJT晶体管的功率级的创建通常相关的问题克服了实现具有BMFET晶体管的功率级。

公开(公告)号：US5245211A

公开(公告)日：1993-09-14

申请号：US605448

申请日：1990-10-30

Applicant: Mario Paparo ,  Sergio Palara

Inventor： Mario Paparo ,  Sergio Palara

IPC: H01L29/74 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04

CPC classification number: H01L27/0248

Abstract: A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).

公开(公告)号：US5227014A

公开(公告)日：1993-07-13

申请号：US435890

申请日：1989-11-14

Applicant: Pier L. Crotti ,  Nadia Iazzi

Inventor： Pier L. Crotti ,  Nadia Iazzi

IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/31116

Abstract: Step coverage in contacts may be improved by forming a tapered hole through a dielectric layer by:a) plasma (RIE) etching through a "contact" mask the dielectric for a depth shorter than the thickness of the layer leaving a residual thickness of dielectric on the bottom of the etch;b) removing the residual masking material;c) conformally depositing a TEOS layer;d) etching the conformally deposited TEOS layer without a mask in (RIE) plasma until exposing the underlying silicon or polysilicon with which the contact must be established.The anisotropic etching of the TEOS layer, conformally deposited on the partially pre-etched dielectric layer, determines a "self-aligned" exposition of the underlying silicon or polysilicon and leaves a tapered TEOS residue on the vertical pre-etched hole's walls, thus providing a desired tapering of the contact hole. Photolithographic definition is no longer a critical factor.

公开(公告)号：US5221886A

公开(公告)日：1993-06-22

申请号：US796687

申请日：1991-11-25

Applicant: Jean M. Pierret ,  Didier Canitrot ,  Alessio Pennisi ,  Fabio Marchio

Inventor： Jean M. Pierret ,  Didier Canitrot ,  Alessio Pennisi ,  Fabio Marchio

IPC: H02J7/16 ,  H02J7/24

CPC classification number: H02J7/244

Abstract: The invention relates to a regulator device for charging a battery by an alternator that delivers a rectified voltage including a ripple component. The device is of the type comprising a regulator circuit acting on the mean value of the rectified alternator voltage and a regulator circuit acting on the voltages of the positive peaks of the ripple component. The regulator circuits are powered by a stabilized voltage derived from the rectified alternator voltage and the device further comprises a power stage for controlling the excitation current of the alternator. According to the invention, the device further includes a regulator circuit acting on the values of the negative peaks of the ripple component. This regulator circuit is also powered by the stabilized voltage, and capable of causing the excitation current to be reduced whenever the voltage of the negative peaks falls below a given threshold.

Abstract translation: 本发明涉及一种用于通过交流发电机对电池进行充电的调节器装置，该交流发电机提供包括纹波分量的整流电压。 该装置的类型包括作用于整流交流发电机电压的平均值的调节器电路和作用在波纹分量的正峰值的电压上的调节器电路。 调节器电路由来自整流交流发电机电压的稳定电压供电，并且该装置还包括用于控制交流发电机的激励电流的功率级。 根据本发明，该装置还包括作用于纹波分量的负峰值的调节器电路。 该调节器电路也由稳定的电压供电，并且能够在负峰值的电压下降到给定阈值以下时使激励电流降低。