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    APPARATUS AND METHODS OF BIT LINE SETUP
    131.
    发明申请
    APPARATUS AND METHODS OF BIT LINE SETUP 有权
    位线设置的装置和方法

    公开(公告)号：US20130033940A1

    公开(公告)日：2013-02-07

    申请号：US13195548

    申请日：2011-08-01

    Applicant: Myung Cho ,  Seong Je Park ,  Jung Hwan Lee

    Inventor： Myung Cho ,  Seong Je Park ,  Jung Hwan Lee

    IPC: G11C16/10 ,  G11C16/06

    CPC classification number: G11C16/06 ,  G11C11/5628 ,  G11C16/26

    Abstract: Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response to the control signal. The apparatus further includes a page buffer configured to provide a bit line voltage to the bit line based on the sense signal and the precharge signal, to thereby control a programming of the memory cell.

    Abstract translation: 公开了方法和装置，包括具有存储单元阵列的装置，存储单元阵列选择性地耦合到位线。 控制电路被配置为提供控制信号。 电压发生器被配置为响应于控制信号提供感测信号和预充电信号。 该装置还包括一个页面缓冲器，其配置为基于感测信号和预充电信号向位线提供位线电压，从而控制存储单元的编程。

    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    134.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    半导体存储器件及其工作方法

    公开(公告)号：US20120236618A1

    公开(公告)日：2012-09-20

    申请号：US13420038

    申请日：2012-03-14

    Applicant: Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

    Inventor： Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

    IPC: G11C15/00

    CPC classification number: G11C15/046 ,  G11C16/10

    Abstract: A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

    Abstract translation: 半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作， 从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到​​的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

    Apparatus and method for controlling power management by comparing tick idle time data to power management state resume time data
    135.
    发明授权
    Apparatus and method for controlling power management by comparing tick idle time data to power management state resume time data 有权
    通过比较怠速时间数据与电源管理状态恢复时间数据来控制电源管理的装置和方法

    公开(公告)号：US08181047B2

    公开(公告)日：2012-05-15

    申请号：US12343196

    申请日：2008-12-23

    Applicant: Jung Hwan Lee

    Inventor： Jung Hwan Lee

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3228 ,  Y02D10/171 ,  Y02D50/20

    Abstract: The present invention relates to an apparatus and a method for controlling power management based on information on ticks for performing program tasks and information on each of power management states, which is applicable to every apparatus and component able to enter a power saving state.By means of entering a corresponding power management based on a result of comparing idle time of a processor during the tick with resume time of each power management state, power consumption can be reduced.

    Abstract translation: 本发明涉及一种用于基于用于执行程序任务的时钟信息和关于每个功率管理状态的信息来控制功率管理的装置和方法，其适用于能够进入省电状态的每个装置和组件。 通过基于比较处理器的空闲时间与每个功率管理状态的恢复时间的比较结果输入相应的功率管理，可以降低功耗。

    APPARATUS AND METHOD USING RADIO SIGNALS
    136.
    发明申请
    APPARATUS AND METHOD USING RADIO SIGNALS 有权
    装置和使用无线电信号的方法

    公开(公告)号：US20120108271A1

    公开(公告)日：2012-05-03

    申请号：US13349135

    申请日：2012-01-12

    Applicant: Jung-Hwan LEE

    Inventor： Jung-Hwan LEE

    IPC: H04W24/00

    CPC classification number: H04W48/08 ,  H04L67/18 ,  H04W4/02

    Abstract: A method of using radio signals transmitted for reception by mobile user equipment that includes receiving, with mobile user equipment (UE), radio signals having at least one format; monitoring, with the mobile user equipment, at least one property of the received radio signals; identifying a pattern in said monitored property or properties; and in response to identifying said pattern, triggering at least one action according to the identified pattern, and/or providing the UE with an indication of a location of the UE based at least part of the identified pattern.

    Abstract translation: 一种使用由移动用户设备接收发送的无线电信号的方法，包括：利用移动用户设备（UE）接收具有至少一种格式的无线电信号; 用移动用户设备监视所接收的无线电信号的至少一个属性; 识别所述监控的属性或属性中的模式; 并且响应于识别所述模式，根据所识别的模式触发至少一个动作，和/或基于所识别的模式的至少一部分向UE提供UE的位置的指示。

    NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME
    137.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME 有权
    非易失存储器件及其读取方法

    公开(公告)号：US20120057409A1

    公开(公告)日：2012-03-08

    申请号：US13183675

    申请日：2011-07-15

    Applicant: Jung Hwan LEE ,  Seong Je PARK

    Inventor： Jung Hwan LEE ,  Seong Je PARK

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C2211/5634 ,  G11C2211/5642

    Abstract: A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.

    Abstract translation: 根据本公开的示例性实施例的非易失性存储器件的读取方法包括预先充电与存储器单元耦合的位线，通过向存储器单元提供第一参考电压来执行第一读取操作，以便确定存储在存储器中的数据 单元，预充电位线，其耦合到其数据尚未被第一读取操作确定的未确定存储单元，以及通过向存储器单元提供第二参考电压来执行第二读取操作，以便确定存储在未确定的存储器单元中的数据。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    138.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20120008416A1

    公开(公告)日：2012-01-12

    申请号：US13177764

    申请日：2011-07-07

    Applicant: Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

    Inventor： Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

    IPC: G11C16/10 ,  G11C16/06

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C29/1201 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2216/14

    Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.

    Abstract translation: 半导体存储器件包括包括多个单元串的存储单元阵列和包括通过位线耦合到各个单元串的多个页缓冲器的页缓冲器组。 每个页面缓冲器包括用于存储要被编程到包括在单元串中的存储器单元中的数据或用于存储从存储器单元读取的数据的锁存单元。 根据在测试操作中存储在锁存单元中的数据，每个页缓冲器被耦合到用于存储器单元的测试操作的焊盘。

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