公开(公告)号：US10796763B2

公开(公告)日：2020-10-06

申请号：US16256525

申请日：2019-01-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/32 ,  G11C16/30 ,  G11C16/10

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

公开(公告)号：US20200302570A1

公开(公告)日：2020-09-24

申请号：US16810486

申请日：2020-03-05

Applicant: STMicroelectronics (Grenoble 20) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Christophe Pinatel ,  Serge Mazer ,  Olivier Ferrand

IPC: G06T1/60 ,  G06T1/20 ,  G06K9/32 ,  G06K9/62 ,  G06N20/00

Abstract: An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.

公开(公告)号：US20200293314A1

公开(公告)日：2020-09-17

申请号：US16886245

申请日：2020-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde

IPC: G06F9/24 ,  G06F8/654 ,  G06F8/656 ,  G06F21/57 ,  G06F13/16 ,  G06F13/38

Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.

公开(公告)号：US10770357B2

公开(公告)日：2020-09-08

申请号：US16429836

申请日：2019-06-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoit Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L29/06 ,  H01L23/522

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US10749572B2

公开(公告)日：2020-08-18

申请号：US16277678

申请日：2019-02-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: H04B5/00 ,  H03K7/08 ,  G06K19/07

Abstract: A circuit includes a near-field communication circuit configured to receive a radio frequency control signal transmitted in a near-field regime, a pulse width modulation signal generation circuit coupled to the near-field communication circuit circuit and configured to generate a pulse width modulation signal according to the radio frequency control signal, and a non-volatile memory coupled to both the near-field communication circuit circuit and the pulse width modulation signal generation circuit, the non-volatile memory comprising digital words for configuring the pulse width modulation signal.

公开(公告)号：US10732894B2

公开(公告)日：2020-08-04

申请号：US15900481

申请日：2018-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/02

Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.

公开(公告)号：US10727239B2

公开(公告)日：2020-07-28

申请号：US16130593

申请日：2018-09-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/11517 ,  H01L29/423 ,  G11C7/18 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/08 ,  G11C16/24

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US10705838B2

公开(公告)日：2020-07-07

申请号：US15607615

申请日：2017-05-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde

IPC: G06F9/44 ,  G06F9/24 ,  G06F8/654 ,  G06F8/656 ,  G06F21/57 ,  G06F13/16 ,  G06F13/38 ,  G06F8/65

Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.

公开(公告)号：US20200184331A1

公开(公告)日：2020-06-11

申请号：US16691914

申请日：2019-11-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/08 ,  G06N20/00 ,  G06F17/16

Abstract: A method can be used to process an initial set of data through a convolutional neural network that includes a convolution layer followed by a pooling layer. The initial set is stored in an initial memory along first and second orthogonal directions. The method includes performing a first filtering of the initial set of data by the convolution layer using a first sliding window along the first direction. Each slide of the first window produces a first set of data. The method also includes performing a second filtering of the first sets of data by the pooling layer using a second sliding window along the second direction.

公开(公告)号：US10672644B2

公开(公告)日：2020-06-02

申请号：US15992481

申请日：2018-05-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/66

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.