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131.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC classification number: H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20230291395A1
公开(公告)日：2023-09-14
申请号：US18176753
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
CPC classification number: H03K5/15066 , H03K5/15093 , H03L7/0996
Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
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133.发明公开公开(公告)号：US20230283252A1
公开(公告)日：2023-09-07
申请号：US18116124
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno LENZ
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/375 , H03F2203/45212
Abstract: An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.
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公开(公告)号：US20230244413A1
公开(公告)日：2023-08-03
申请号：US17810093
申请日：2022-06-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Jawad Benhammadi
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0679
Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.
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公开(公告)号：US20230239057A1
公开(公告)日：2023-07-27
申请号：US18150115
申请日：2023-01-04
Inventor： Nicolas MOENECLAEY , Vratislav MICHAL , Jean-Luc PATRY
IPC: H04B10/61
CPC classification number: H04B10/616
Abstract: The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.
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Patent Agency Ranking
公开(公告)号：US20230228554A1
公开(公告)日：2023-07-20
申请号：US18147927
申请日：2022-12-29
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Santi Carlo Adamo , Cyril Joubert , Bastien Mahtal , Damien Giot , Hugo Gicquel , Alexandre Gimard
Abstract: An electronic system includes a first LC oscillator connected to a first general-purpose input/output (GPIO) circuit and a second LC oscillator connected to a second GPIO circuit. A threshold generator is coupled to an input of the comparator. A control circuit is configured to control a measurement phase comprising a first capture phase and a second capture phase. A microcontroller is coupled to the control circuit and a power management circuit is configured to switch-off the microcontroller following activation of the control circuit by the microcontroller. The control circuit is configured to control the application of an excitation signal to the each oscillator via the respective GPIO circuit, control the GPIO circuit so that oscillations of the oscillator are provided to the comparator, and count, based on an output of the comparator, a number of oscillations in the oscillator exceeding a threshold output by the threshold generator.
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公开(公告)号：US20230221420A1
公开(公告)日：2023-07-13
申请号：US18093210
申请日：2023-01-04
Applicant: STMicroelectronics (Alps) SAS
Inventor： Xavier BRANCA
IPC: G01S7/4865 , G01J1/44 , H02M3/155 , G01J1/02
CPC classification number: G01S7/4865 , G01J1/44 , H02M3/1552 , G01J1/0219 , G01J2001/442 , G01J2001/4466
Abstract: A light sensor includes an integrated circuit chip and a boost DC/DC converter. The integrated circuit chip supports an array of pixels, each pixel including a SPAD. The boost DC/DC converter delivers to the SPADs a bias potential capable of placing the SPADs in Geiger mode. The boost DC/DC converter includes an inductive element, a first switch, a second switch, and a circuit for controlling on/off switching of the first switch. The inductive element and the first and second switches are arranged outside of the integrated circuit chip while the control circuit forms part of the integrated circuit chip.
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公开(公告)号：US20230213577A1
公开(公告)日：2023-07-06
申请号：US18181128
申请日：2023-03-09
Inventor： Etienne Auvray , Tommaso Melis , Philippe Sirito-Olivier
IPC: G01R31/311 , G01R15/22 , G01R19/00 , G01R31/28
CPC classification number: G01R31/311 , G01R15/22 , G01R19/0084 , G01R31/2851
Abstract: According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.
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公开(公告)号：US11676928B2
公开(公告)日：2023-06-13
申请号：US17396346
申请日：2021-08-06
Inventor： Romain Coffy , Patrick Laurent , Laurent Schwartz
CPC classification number: H01L24/24 , H01L21/56 , H01L23/3185 , H01L24/05 , H01L24/16 , H01L24/73 , H01L24/82 , H01L2224/0233 , H01L2224/02315 , H01L2224/02381 , H01L2224/16145 , H01L2224/24011 , H01L2224/24105 , H01L2224/24137 , H01L2224/24195 , H01L2224/24226 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2224/82048 , H01L2224/82108
Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
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公开(公告)号：US20230161485A1
公开(公告)日：2023-05-25
申请号：US17993618
申请日：2022-11-23
Inventor： Loic Pallardy , Nicolas Anquet
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.
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