公开(公告)号：US12223989B2

公开(公告)日：2025-02-11

申请号：US18151994

申请日：2023-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  G11C5/02 ,  G11C5/06 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US12223252B2

公开(公告)日：2025-02-11

申请号：US18171072

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheng-Hung Yeh ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Yi-Kan Cheng ,  Hsiu-Chuan Shu

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US12222654B2

公开(公告)日：2025-02-11

申请号：US17378507

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/40

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US20250048716A1

公开(公告)日：2025-02-06

申请号：US18365763

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen Chuang ,  Ji-Yin Tsai ,  Jet-Rung Chang ,  Zheng Hui Lim ,  Ta-Chun Ma

IPC: H01L21/8238 ,  H01L29/66

Abstract: Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.

公开(公告)号：US20250046734A1

公开(公告)日：2025-02-06

申请号：US18490014

申请日：2023-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hung Lin ,  Chi-Chun Hsieh ,  Ming-Hua Lo ,  Chung-Chih Chen ,  Hsin-Hsien Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. A diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.

公开(公告)号：US20250046655A1

公开(公告)日：2025-02-06

申请号：US18524386

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chao Yi Lin ,  Kuo-Yen Liu ,  Chih-Hsiang Yao

IPC: H01L21/768 ,  G06F30/392 ,  H01L23/58

Abstract: A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.

公开(公告)号：US20250044532A1

公开(公告)日：2025-02-06

申请号：US18352655

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang Shao ,  Yu-Sheng Huang ,  Chen-Hua Yu

IPC: G02B6/42

Abstract: A package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a bottom surface of the transparent block is nonplanar, wherein the second waveguide is a fixed distance from the bottom surface along its length, wherein the second waveguide is optically coupled to the first waveguide.

公开(公告)号：US20250044530A1

公开(公告)日：2025-02-06

申请号：US18526920

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chih-Tsung Tsai ,  Kuo Chin Hsu

IPC: G02B6/42

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized with an optical interposer. In embodiments a method patterns a substrate to form a recess with a sidewall, forms a mirror coating on the sidewall, deposits and patterns a material to form a first waveguide adjacent to the mirror coating, and bonds an optical interposer over the first waveguide.

公开(公告)号：US20250044517A1

公开(公告)日：2025-02-06

申请号：US18365050

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Jen Wang ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Chen-Hua Yu

IPC: G02B6/30 ,  G02B6/32

Abstract: A package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a first end of the second waveguide is optically coupled to the first waveguide, wherein the waveguide structure is configured to be connected to an optical fiber component such that a second end of the second waveguide is optically coupled to an optical fiber of the optical fiber component.

公开(公告)号：US12219880B2

公开(公告)日：2025-02-04

申请号：US18595256

申请日：2024-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.