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公开(公告)号：US09705458B1
公开(公告)日：2017-07-11
申请号：US14812405
申请日：2015-07-29
Applicant: Cirrus Logic, Inc.
Inventor： John Christopher Tucker , Daniel John Allen , John L. Melanson , Ammisetti Prasad
CPC classification number: H03G3/004 , H02M3/07 , H03F1/0227 , H03F1/025 , H03F3/183 , H03F2200/03 , H03F2200/211 , H03F2200/507 , H03G3/20 , H03G3/3031
Abstract: An energy-efficient consumer device audio power output stage with gain control provides improved battery life and reduced power dissipation without clipping the audio output signal. A control circuit controls a power supply that supplies the power supply rails to the power amplified output stage. The voltage of the power supply rails is controlled in conformity with an input audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The gain applied to the audio input signal is reduced for a predetermined time period when a higher output voltage of the power supply is selected, to avoid clipping the audio output signal.
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公开(公告)号：US09680488B2
公开(公告)日：2017-06-13
申请号：US15050857
申请日：2016-02-23
Applicant: Cirrus Logic, Inc.
Inventor： Tejasvi Das , John L. Melanson , John C. Tucker , Xiaofan Fei
CPC classification number: H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
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公开(公告)号：US09628033B2
公开(公告)日：2017-04-18
申请号：US14840894
申请日：2015-08-31
Applicant: Cirrus Logic, Inc.
Inventor： Eric J. King , Christophe J. Amadi , John L. Melanson
CPC classification number: H03F3/2175 , H03F1/0277 , H03F1/083 , H03F3/181 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2178 , H03F2200/03 , H03F2200/231
Abstract: A method for producing an output voltage to a load may include, in a power stage comprising power converter having a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, and an output for producing the output voltage comprising a first output terminal and a second output terminal, controlling the linear amplifier to transfer electrical energy from the input source of the power stage to the load in accordance with one or more least significant bits of a digital input signal, and controlling the power converter in accordance with bits of the digital input signal other than the one or more least significant bits to sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from the input source of the power stage to the load.
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134.发明授权公开(公告)号：US09571931B1
公开(公告)日：2017-02-14
申请号：US14247987
申请日：2014-04-08
Applicant: Cirrus Logic, Inc.
Inventor： John L. Melanson , John C. Tucker
CPC classification number: H04R3/02 , H03F1/26 , H03F3/16 , H03F2200/372 , H03M3/00 , H03M3/39 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026 , H03M7/3028 , H04R3/00 , H04R3/002 , H04R3/007 , H04R19/04 , H04R29/001
Abstract: To correct for non-linearities in the response of a microphone as a function of sound pressure level incident upon the microphone, a displacement non-linearity function is applied to the signal path of the microphone, wherein the displacement non-linearity function is a function of the digital audio output signal and has a response modeling non-linearities of the displacement as a function of a sound pressure level incident upon the microphone.
Abstract translation: 为了校正麦克风的响应中的非线性作为入射到麦克风的声压级的函数，位移非线性函数被施加到麦克风的信号路径，其中位移非线性函数是函数 的数字音频输出信号，并且具有作为入射到麦克风的声压级的函数的位移的非线性的响应建模。
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公开(公告)号：US09419562B1
公开(公告)日：2016-08-16
申请号：US14248054
申请日：2014-04-08
Applicant: Cirrus Logic, Inc.
Inventor： John L. Melanson , John C. Tucker
CPC classification number: H04R3/02 , H03F1/26 , H03F3/16 , H03F2200/372 , H03M3/00 , H03M3/39 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026 , H03M7/3028 , H04R3/00 , H04R3/002 , H04R3/007 , H04R19/04 , H04R29/001
Abstract: An amplifier may include a plurality of stages, wherein each stage may have an amplifier stage output configured to generate an amplifier output signal and a transistor coupled at its gate terminal to the amplifier input and to the gate terminals of the transistors of the other amplifier stages. Each stage may be configured to periodically and cyclically operate in an amplifier mode in which the amplifier stage generates at its corresponding amplifier stage output a power-amplified version of a signal received at the amplifier input and a in reset mode in which the transistor of the stage operating in the reset mode has an electrical property thereof reset. At any given time, at least one amplifier stage is operating in the amplifier mode. The amplifier may be configured to output as an output signal one of the amplifier output signals corresponding to an amplifier stage operating in the amplifier mode.
Abstract translation: 放大器可以包括多个级，其中每个级可以具有被配置为产生放大器输出信号的放大器级输出和在其栅极端耦合到放大器输入端和耦合到其它放大器级的晶体管的栅极端子的晶体管 。 每个级可以被配置为在放大器模式中周期性地和周期性地工作，其中放大器级在其相应的放大级产生输出在放大器输入处接收的信号的功率放大形式，在复位模式中， 在复位模式下工作的电平具有电性能的复位。 在任何给定时间，至少一个放大器级在放大器模式下工作。 放大器可以被配置为输出对应于以放大器模式工作的放大器级的放大器输出信号之一作为输出信号。
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Patent Agency Ranking
公开(公告)号：US09379732B2
公开(公告)日：2016-06-28
申请号：US14845899
申请日：2015-09-04
Applicant: Cirrus Logic, Inc.
Inventor： John L. Melanson , Stephen T. Hodapp
Abstract: Requirements placed on the first integrator of a filter in a continuous-time delta-feedback modulator may be reduced by using circuitry to reduce the speed of a signal provided to the first integrator of the modulator. The reduction in speed applied to the signal received at the first integrator may then be compensated with circuitry elsewhere in the modulator, such that the net effect of the slow down and speed up of signals does not affect the output of the modulator. The sigma-delta modulator may be implemented in converters, such as an analog-to-digital converter (ADC).
Abstract translation: 通过使用电路来降低提供给调制器的第一积分器的信号的速度，可以减少在连续时间增量反馈调制器中对滤波器的第一积分器的要求。 然后可以利用在调制器其他地方的电路补偿施加到在第一积分器处接收的信号的速度的降低，使得信号的减速和加速的净效应不影响调制器的输出。 Σ-Δ调制器可以在诸如模数转换器（ADC）的转换器中实现。
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137.发明授权公开(公告)号：US09368099B2
公开(公告)日：2016-06-14
申请号：US14228322
申请日：2014-03-28
Applicant: Cirrus Logic, Inc.
Inventor： Jeffrey Alderson , Nitin Kwatra , Gautham Devendra Kamath , Ali Abdollahzadeh Milani , John L. Melanson
IPC: G10K11/16 , G10K11/178
CPC classification number: G10K11/178 , G10K2210/108 , G10K2210/1081 , G10K2210/1082 , G10K2210/3017 , G10K2210/3028 , G10K2210/3035 , G10K2210/3049 , G10K2210/3056 , G10K2210/511
Abstract: A personal audio device, such as a wireless telephone, includes noise canceling circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone may also be provided proximate the speaker to measure the output of the transducer in order to control the adaptation of the anti-noise signal and to estimate an electro-acoustical path from the noise canceling circuit through the transducer. A processing circuit that performs the adaptive noise canceling (ANC) function also either adjusts the frequency response of the anti-noise signal with respect to the reference microphone signal, and/or by adjusting the response of the adaptive filter independent of the adaptation provided by the reference microphone signal.
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公开(公告)号：US20160126908A1
公开(公告)日：2016-05-05
申请号：US14840894
申请日：2015-08-31
Applicant: Cirrus Logic, Inc.
Inventor： Eric J. King , Christophe J. Amadi , John L. Melanson
IPC: H03F3/217
CPC classification number: H03F3/2175 , H03F1/0277 , H03F1/083 , H03F3/181 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2178 , H03F2200/03 , H03F2200/231
Abstract: A method for producing an output voltage to a load may include, in a power stage comprising power converter having a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, and an output for producing the output voltage comprising a first output terminal and a second output terminal, controlling the linear amplifier to transfer electrical energy from the input source of the power stage to the load in accordance with one or more least significant bits of a digital input signal, and controlling the power converter in accordance with bits of the digital input signal other than the one or more least significant bits to sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from the input source of the power stage to the load.
Abstract translation: 用于向负载产生输出电压的方法可以包括在包括具有功率电感器的功率转换器的功率级中，布置成以多个开关配置顺序工作的多个开关，以及用于产生包括 第一输出端和第二输出端，控制线性放大器根据数字输入信号的一个或多个最低有效位将电能从功率级的输入源传输到负载，并根据 其中所述数字输入信号的位与所述一个或多个最低有效位不同，以顺序地施加来自所述多个开关配置的开关配置以选择性地激活或去激活所述多个开关中的每一个，以便从所述多个开关的输入源 功率级到负载。
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139.发明授权公开(公告)号：US09325434B2
公开(公告)日：2016-04-26
申请号：US14276237
申请日：2014-05-13
Applicant: Cirrus Logic, Inc.
Inventor： John L. Melanson , John C. Tucker
CPC classification number: H04B15/04 , G05B15/02 , G05F1/14 , G06F1/08 , G06F3/165 , H04B2215/067 , H04B2215/068
Abstract: A mobile device may include a digital data driver and digital data receiver for communication of digital signals within the mobile device at a selected clock rate. The mobile device may also have a device external for the digital data driver and digital data receiver for communication of external signals, such as radio-frequency signals, to and from the mobile device. To avoid interference of frequency harmonics of a digital signal with such external signals, the digital data driver may be configured to control the digital signal based on the frequency of the external signals, such that interference of the external signal by spectral content of the digital signal is minimized, while maintaining the selected clock rate.
Abstract translation: 移动设备可以包括数字数据驱动器和数字数据接收器，用于以选定的时钟速率在移动设备内通信数字信号。 移动设备还可以具有用于数字数据驱动器的外部设备和数字数据接收器，用于将外部信号（例如射频信号）传送到移动设备和从移动设备通信。 为了避免数字信号与这种外部信号的频率谐波的干扰，数字数据驱动器可以被配置为基于外部信号的频率来控制数字信号，使得通过数字信号的频谱内容对外部信号的干扰 同时保持选定的时钟频率。
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公开(公告)号：US09306588B2
公开(公告)日：2016-04-05
申请号：US14680830
申请日：2015-04-07
Applicant: Cirrus Logic, Inc.
Inventor： Tejasvi Das , John L. Melanson , John C. Tucker , Xiaofan Fei
CPC classification number: H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
Abstract translation: 根据本公开的实施例，处理系统可以包括多个处理路径，包括第一处理路径和第二处理路径，数模转换阶段输出和控制器。 第一处理路径可以包括用于将数字输入信号转换成第一中间模拟信号的第一数模转换器，第一数模转换器被配置为在大功率状态和低功率状态 。 第二处理路径可以包括用于将数字输入信号转换成第二中间模拟信号的第二数模转换器。 数模转换级输出可以被配置为产生包括第一中间模拟信号和第二中间模拟信号之和的模拟信号。 控制器可以被配置为当数字输入信号的幅度低于阈值大小时，在较低功率状态下操作第一数模转换器。
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