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260 条记录 (耗时 0.035 秒)

    METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS
    133.
    发明申请
    METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS 有权
    用于监测雕刻开口的完整性和形成具有开口的导电结构的方法

    公开(公告)号：US20090255818A1

    公开(公告)日：2009-10-15

    申请号：US12101329

    申请日：2008-04-11

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L21/288

    CPC分类号： H01L21/76879 ,  C25D5/10 ,  C25D5/12 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76802 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.

    摘要翻译： 公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等） 。）在这样的开口内。 该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。 具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。 然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。

    Method of fabricating self-aligned bipolar transistor having tapered collector
    135.
    发明申请
    Method of fabricating self-aligned bipolar transistor having tapered collector 有权
    制造具有锥形集电极的自对准双极晶体管的方法

    公开(公告)号：US20080318373A1

    公开(公告)日：2008-12-25

    申请号：US12220521

    申请日：2008-07-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有 比下表面小得多的面积。 收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

    Electrically programmable π-shaped fuse structures and methods of fabrication thereof
    136.
    发明授权
    Electrically programmable π-shaped fuse structures and methods of fabrication thereof 有权
    电气可编程的pi形熔丝结构及其制造方法

    公开(公告)号：US07288804B2

    公开(公告)日：2007-10-30

    申请号：US11372380

    申请日：2006-03-09

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L27/10

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a α-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

    摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝，第一支撑件和第二支撑件在通过熔断元件的正面横截面中限定了α形结构。 第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

    Voltage divider for integrated circuits
    138.
    发明授权
    Voltage divider for integrated circuits 失效
    用于集成电路的分压器

    公开(公告)号：US07061308B2

    公开(公告)日：2006-06-13

    申请号：US10605466

    申请日：2003-10-01

    申请人： Wagdi W. Abadeer ,  John A. Fifield ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  John A. Fifield ,  William R. Tonti

    IPC分类号： G05F3/02

    CPC分类号： G11C5/147 ,  H01L27/0802 ,  H01L27/088 ,  H02M3/00

    摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).

    摘要翻译： 用于集成电路的分压器，不包括使用电阻器。 在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET 1和NFET 2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A 1（未示出）的栅电极（16）和p-衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A 2（未示出）的栅电极（24）和p基板（26）。 NFET 1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET 1和NFET 2之间的电压差与VDD具有线性关系。 结果，通过适当地选择各个晶体管栅电极区域（A 1）和（A 2）之间的比率，可以在NFET 1和NFET 2之间划分电压VDD。

    Antifuse with electrostatic assist
    139.
    发明授权
    Antifuse with electrostatic assist 失效
    防静电辅助

    公开(公告)号：US06844609B2

    公开(公告)日：2005-01-18

    申请号：US10278431

    申请日：2002-10-23

    申请人： William T. Motsiff ,  William R. Tonti ,  Richard Q. Williams

    发明人： William T. Motsiff ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L21/44

    CPC分类号： H01L23/5252 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

    摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

    MOSFET with decoupled halo before extension
    140.
    发明授权
    MOSFET with decoupled halo before extension 有权
    扩展前分离光环的MOSFET

    公开(公告)号：US06730552B1

    公开(公告)日：2004-05-04

    申请号：US10604096

    申请日：2003-06-26

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

    摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

    摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。