公开(公告)号：US10290544B2

公开(公告)日：2019-05-14

申请号：US15728632

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Chanro Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L23/528

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

公开(公告)号：US10211147B2

公开(公告)日：2019-02-19

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US20190035938A1

公开(公告)日：2019-01-31

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US20190013269A1

公开(公告)日：2019-01-10

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US10177241B2

公开(公告)日：2019-01-08

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

公开(公告)号：US09966456B1

公开(公告)日：2018-05-08

申请号：US15345644

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09953879B1

公开(公告)日：2018-04-24

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US09911619B1

公开(公告)日：2018-03-06

申请号：US15291446

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Catherine B. Labelle ,  Lars W. Liebmann ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs). A first plurality of hardmask sections may be formed, and sacrificial spacers may be formed on vertical sidewalls of the first plurality of hardmask sections. Each of the first plurality of hardmask sections is comprised of a first material. Gaps between the sacrificial spacers are filled with a second material, which is selected to etch selectively to the first material, in order to define a second plurality of hardmask sections each comprised of the second material.

公开(公告)号：US09899321B1

公开(公告)日：2018-02-20

申请号：US15373691

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L23/528 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/7684 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/66553

Abstract: One illustrative method disclosed includes, among other things, completely forming a first conductive structure comprising one of a conductive gate contact structure (CB) or a conductive source/drain contact structure (CA), wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of an active region of a transistor device, and, after completely forming the first conductive structure, completely forming a second conductive structure comprising the other of the conductive gate contact structure (CB) or the conductive source/drain contact structure (CA).

公开(公告)号：US20180047564A1

公开(公告)日：2018-02-15

申请号：US15233445

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L21/027 ,  H01L21/306 ,  H01L21/263

CPC classification number: H01L21/263 ,  H01L21/0338 ,  H01L21/31122 ,  H01L21/31144

Abstract: A novel method of processing and fabricating semiconductor devices is provided to reduce critical dimensions inherent in a given photolithography process. A patterned mask layer generated via transfer of the pattern to the masking layer (e.g., printing) has a given set of dimensions. The method or process forms multiple layers beneath a masking layer. The multiple layers are etched to form openings therein according to the original mask pattern. Thereafter, one of the multiple layers is etched along its sidewalls to increase the opening therethrough, and this layer is utilized as the mask layer for the underlying semiconductor substrate. This enables a reduction in the critical dimensions, at least a critical dimension related to spacing between two features.