公开(公告)号：US20230395518A1

公开(公告)日：2023-12-07

申请号：US18451156

申请日：2023-08-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.

公开(公告)号：US11804455B1

公开(公告)日：2023-10-31

申请号：US17960057

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Thomas Sounart ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prithwish Chatterjee ,  Andrew J. Brown

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/642 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/19041 ,  H01L2924/19103

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US11715693B2

公开(公告)日：2023-08-01

申请号：US16397923

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Henning Braunisch ,  Johanna M. Swan ,  Telesphor Kamgaing

IPC: H01L23/538 ,  H01L23/66 ,  G02B6/30 ,  H01P3/16 ,  H01P11/00

CPC classification number: H01L23/538 ,  G02B6/30 ,  H01L23/66 ,  H01P3/16 ,  H01P11/006 ,  H01L2223/6627

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US11688660B2

公开(公告)日：2023-06-27

申请号：US16534820

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01Q23/00 ,  H01Q1/52 ,  H01Q1/02 ,  H01L23/36 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/36 ,  H01L23/5381 ,  H01L23/552

Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.

公开(公告)号：US11621236B2

公开(公告)日：2023-04-04

申请号：US16728278

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/34 ,  H01L23/498 ,  H01L23/532 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.

公开(公告)号：US20230095608A1

公开(公告)日：2023-03-30

申请号：US17485250

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Henning Braunisch ,  Thomas L. Sounart ,  Johanna Swan ,  Beomseok Choi ,  Krishna Bharath ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H05K3/14 ,  H05K3/10 ,  H05K3/30 ,  H01L21/768 ,  H01L21/82

Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

公开(公告)号：US11605603B2

公开(公告)日：2023-03-14

申请号：US16397718

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/66

Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US20220415743A1

公开(公告)日：2022-12-29

申请号：US17358361

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Aleksandar Aleksov ,  Julien Sebot

IPC: H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06 ,  H01L23/00

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

公开(公告)号：US11538803B2

公开(公告)日：2022-12-27

申请号：US16221086

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Telesphor Kamgaing ,  Aleksandar Aleksov ,  Gerogios Dogiamis ,  Hyung-Jin Lee

IPC: H01L29/40 ,  H01L21/00 ,  H01L27/07 ,  H01L21/8238 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

公开(公告)号：US11462480B2

公开(公告)日：2022-10-04

申请号：US16020295

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/13 ,  H01L25/00 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.