公开(公告)号：US20200006236A1

公开(公告)日：2020-01-02

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US10475736B2

公开(公告)日：2019-11-12

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US10361142B2

公开(公告)日：2019-07-23

申请号：US15625947

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Don W. Nelson

IPC: H01L23/367 ,  H01L23/473 ,  H01L21/52 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/18 ,  H01L23/36

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

公开(公告)号：US20170280568A1

公开(公告)日：2017-09-28

申请号：US15621403

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Henning Braunisch

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K3/0082 ,  H05K1/116 ,  H05K3/422 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4679 ,  H05K2201/09463 ,  H05K2201/09854 ,  H05K2203/0505

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

公开(公告)号：US20170187419A1

公开(公告)日：2017-06-29

申请号：US14998254

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Zhang ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Henning Braunisch ,  Kemal Aygun

IPC: H04B3/32 ,  H04L5/14

CPC classification number: H04B3/32 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.

公开(公告)号：US09093990B2

公开(公告)日：2015-07-28

申请号：US14031438

申请日：2013-09-19

Applicant: Intel Corporation

Inventor： Henning Braunisch

IPC: H03K17/16 ,  H03K3/013 ,  H03K19/00

CPC classification number: H03K3/013 ,  H03K19/0005

Abstract: This disclosure relates generally to devices, systems, and methods that include conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the conductive lines are coupled. The devices, systems, and methods further include a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the conductive lines, a source impedance matrix of the source impedance being substantially proportional to the characteristic impedance matrix of the plurality of conductive lines.

Abstract translation: 本公开一般涉及包括被配置为在第一电子部件和第二电子部件之间传输电信号的导线的装置，系统和方法，在该第二电子部件与第二电子部件之间连接有导线。 所述装置，系统和方法还包括被配置为产生电信号的发射器，所述发射器至少部分地基于所述导线中各导体之间的电阻耦合，所述发射器包括源阻抗，所述源阻抗矩阵 源阻抗基本上与多条导线的特性阻抗矩阵成比例。