公开(公告)号：US09542522B2

公开(公告)日：2017-01-10

申请号：US14491693

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L23/48 ,  H01L21/336 ,  G06F17/50 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09515017B2

公开(公告)日：2016-12-06

申请号：US14943880

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/52 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路（IC）组件中用于串扰缓解的地面通过群集的技术和配置。 在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。 第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和相同的通孔层的至少两个接地通孔，并且所述至少两个接地通孔可以形成一组接地通孔， 个人联系。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160300803A1

公开(公告)日：2016-10-13

申请号：US15187737

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/08 ,  H01L23/50 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

公开(公告)号：US20160276091A1

公开(公告)日：2016-09-22

申请号：US14664827

申请日：2015-03-21

Applicant: INTEL CORPORATION

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC: H01F27/28 ,  H05K3/30 ,  H05K1/11 ,  H01F41/04 ,  H05K1/18

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/165

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US20160104632A1

公开(公告)日：2016-04-14

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 这里描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。