公开(公告)号：US06504200B2

公开(公告)日：2003-01-07

申请号：US09951243

申请日：2001-09-12

申请人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

发明人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

公开(公告)号：US06475866B2

公开(公告)日：2002-11-05

申请号：US09774316

申请日：2001-01-31

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

IPC分类号： H01L21336

CPC分类号： H01L27/112 ,  G11C11/5692 ,  H01L27/11273

摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).

摘要翻译： 一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。 通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。 可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

公开(公告)号：US06445046B1

公开(公告)日：2002-09-03

申请号：US09331034

申请日：1999-06-15

申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul Werner von Basse ,  Wolfgang Krautschneider

发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul Werner von Basse ,  Wolfgang Krautschneider

IPC分类号： H01L29772

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11517

摘要： A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.

摘要翻译： 多个彼此绝缘的存储器单元线路，并且分别包括第一掺杂区域和第二掺杂区域，在该第二掺杂区域和第二掺杂区域之间包含具有电荷载流子阱的材料和多个栅电极的栅极电介质。 相邻栅电极的间隔小于栅电极的尺寸。 通过将电荷载体引入栅极电介质来存储信息。 优选地，通过间隔物技术来制造栅电极。

公开(公告)号：US06399433B2

公开(公告)日：2002-06-04

申请号：US09773218

申请日：2001-01-31

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/55

摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.

摘要翻译： 一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。 在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。 在该间隙中形成单元板电极，并在该层中形成沟槽。 沟槽达到第一插头表面的最远处，并且填充有绝缘层。 该层被删除。 形成具有高ε或铁电介质的存储电容器和存储节点电极。 电容器设置在身体内和上方的第二平面内。 绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。 第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

公开(公告)号：US06365888B2

公开(公告)日：2002-04-02

申请号：US09782733

申请日：2001-02-13

申请人： Paul-Werner Von Basse ,  Josef Willer ,  Thomas Scheiter ,  Stephan Marksteiner

发明人： Paul-Werner Von Basse ,  Josef Willer ,  Thomas Scheiter ,  Stephan Marksteiner

IPC分类号： H01L2700

CPC分类号： G06K9/0002

摘要： A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

摘要翻译： 导体区域的格子阵列用于电容图像采集。 每个壳体中的屏蔽导体都设置在用于测量的导体之间。 在多个充电和放电循环期间，为了防止屏蔽电容器之间的位移电流，电势总是沿着属于相应像素的导体承载。 作为示例，具有反馈运算放大器的补偿线可以用于相同地改变导体上的电位。

公开(公告)号：US06265748B1

公开(公告)日：2001-07-24

申请号：US09180129

申请日：1998-11-02

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

IPC分类号： H01L2976

CPC分类号： H01L27/112 ,  G11C11/5692 ,  H01L27/11273

摘要： A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

摘要翻译： 一种存储单元布置及其制造方法，其包括作为存储单元的垂直MOS晶体管，其中通过多级编程通过晶体管的至少三个不同的阈值电压值来存储信息。 通过厚氧化物晶体管的栅极电介质的厚度获得一个阈值电压值，并且通过不同的沟道掺杂获得其它阈值电压值。 可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

公开(公告)号：US06242319B1

公开(公告)日：2001-06-05

申请号：US09498530

申请日：2000-02-04

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L2176

CPC分类号： H01L27/10858 ,  H01L23/544 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first structure of a circuit configuration and a first alignment structure are produced in the region of a surface of a first substrate. The first alignment structure scatters electron beams differently than its surroundings. A second substrate, which is more transmissive to electron beams than the first alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align a mask with respect to the first structure, a position of the first alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an uncovered upper surface of the second substrate. The first structure may be a metallic line encapsulated by insulating material. A contact may connect the first structure to the second structure. With the aid of electron beam lithography, at least one second alignment structure may be produced in the region of the upper surface of the second substrate, using which the mask is aligned.

摘要翻译： 在第一基板的表面的区域中制造电路结构和第一对准结构的第一结构。 第一对准结构与其周围环境不同地散射电子束。 与第一对准结构相比，对电子束更透射的第二衬底以这样的方式连接到第一衬底，使得第二衬底设置在第一衬底的表面之上。 为了使掩模相对于第一结构对准，借助于电子束来确定第一对准结构的位置。 借助于掩模，在第二基板的未覆盖的上表面的区域中产生电路构造的至少一个第二结构。 第一结构可以是由绝缘材料包封的金属线。 触点可以将第一结构连接到第二结构。 借助于电子束光刻技术，可以在第二衬底的上表面的区域中产生至少一个第二对准结构，使用掩模进行对准。

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

申请人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

发明人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US5347696A

公开(公告)日：1994-09-20

申请号：US164719

申请日：1993-12-10

申请人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

发明人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

IPC分类号： C23F4/00 ,  H01G4/30 ,  H01L21/822 ,  H01L27/04 ,  H01G4/10

CPC分类号： H01G4/306 ,  Y10T29/435

摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).

摘要翻译： 为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层 （2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。 在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在 所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

公开(公告)号：US4931136A

公开(公告)日：1990-06-05

申请号：US390642

申请日：1989-08-07

申请人： Thomas Pausch ,  Josef Willer

发明人： Thomas Pausch ,  Josef Willer

IPC分类号： H01L21/302 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/338 ,  H01L29/812

CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L21/32136 ,  H01L21/32137

摘要： This invention relates to a method and apparatus for manufacturing a metal contact with overhanging upper edges. The metal contact has at least one specific layer tapering away from the surface of a semiconductor layer structure. The metal contact is formed by RIE and mask technology, in which a concavely formed equipotential boundary surface is formed between an anode and a cathode. In a preferred embodiment, the curvature is achieved by selecting the effective areas of the cathode and anode so that their rate is no greater than 3:4.

摘要翻译： 本发明涉及一种用于制造具有突出的上边缘的金属接触的方法和装置。 金属接触件具有至少一个比半导体层结构的表面逐渐变细的特定层。 金属接触通过RIE和掩模技术形成，其中在阳极和阴极之间形成凹形的等电势边界表面。 在优选实施例中，通过选择阴极和阳极的有效面积使得它们的速率不大于3:4来实现曲率。