公开(公告)号：US20150262673A1

公开(公告)日：2015-09-17

申请号：US14725619

申请日：2015-05-29

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/06 ,  G11C16/26

Abstract: Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

Abstract translation: 公开了装置和方法，包括具有耦合到公共源的电荷存储装置串的装置，耦合在电荷存储装置串和负载电流源之间的第一开关和耦合在负载电流源和 共同的来源。 描述附加的装置和方法。

公开(公告)号：US20150200590A1

公开(公告)日：2015-07-16

申请号：US14667442

申请日：2015-03-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H02M3/07 ,  G11C16/30

CPC classification number: H02M3/07 ,  G11C16/30 ,  H02M1/36 ,  H02M3/073

Abstract: Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and a cut-off switch circuit arranged to reduce leakage current from the charge pump circuit. The cut-off switch circuit includes a second transistor, wherein an output of the charge pump circuit is coupled to one of a source node and a drain node of the second transistor, and a first control signal is input at a gate of the second transistor. Further embodiments provide a method for generating voltage. One such method includes enabling a first transistor coupled to an output of a charge pump circuit when the charge pump is operating and disabling the first transistor coupled to the output of the charge pump circuit when the charge pump circuit is not operating.

公开(公告)号：US20140375348A1

公开(公告)日：2014-12-25

申请号：US13922378

申请日：2013-06-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G01R31/26

CPC classification number: G11C29/50 ,  G01R31/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C29/025 ,  G11C29/08 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5004

Abstract: In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.

Abstract translation: 在一个实施例中，短检查方法包括在激活耦合到数据线的存储器单元的同时将数据线充电到初始电压，从而允许数据线在继续激活存储器单元的同时浮动，感测数据上产生的电压 在一定时间之后，确定是否存在响应于所得电压的电平的短路。

公开(公告)号：US20140112078A1

公开(公告)日：2014-04-24

申请号：US14142551

申请日：2013-12-27

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有耦合到存储器单元串的数据线的装置和被配置为选择性地将数据线中的一个耦合到节点的选择器。 存储单元串和选择器可以形成在设备的相同存储器阵列中。 描述包括附加装置和方法的其它实施例。

公开(公告)号：US20130336068A1

公开(公告)日：2013-12-19

申请号：US13971626

申请日：2013-08-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C7/00

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.

公开(公告)号：US20230015491A1

公开(公告)日：2023-01-19

申请号：US17936445

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US20220359554A1

公开(公告)日：2022-11-10

申请号：US17872511

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US20210134373A1

公开(公告)日：2021-05-06

申请号：US17149048

申请日：2021-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  H01L27/115

Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

公开(公告)号：US10998054B2

公开(公告)日：2021-05-04

申请号：US16700641

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US20210035995A1

公开(公告)日：2021-02-04

申请号：US17027399

申请日：2020-09-21

Applicant: : Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11575

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.