公开(公告)号：US12197745B2

公开(公告)日：2025-01-14

申请号：US17817711

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

公开(公告)号：US20240153564A1

公开(公告)日：2024-05-09

申请号：US17981919

申请日：2022-11-07

Applicant: Macronix International Co., Ltd.

Inventor： Wei-Han Chen ,  Chun-Hsiung Hung

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

公开(公告)号：US20230377633A1

公开(公告)日：2023-11-23

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/063

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US11301151B2

公开(公告)日：2022-04-12

申请号：US16870848

申请日：2020-05-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: G06F3/06 ,  H01L25/065

Abstract: A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.

公开(公告)号：US11258599B2

公开(公告)日：2022-02-22

申请号：US16793986

申请日：2020-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Chen-Chia Fan

IPC: H04L9/08 ,  H04L9/32 ,  G06F21/62 ,  G06F3/06 ,  G06F12/0877

Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

公开(公告)号：US11132176B2

公开(公告)日：2021-09-28

申请号：US16359919

申请日：2019-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shang-Chi Yang

IPC: G06F7/544 ,  G11C16/24 ,  G11C16/08 ,  G11C11/56 ,  G11C16/04

Abstract: An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash array, storing weight values Wi,n. A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. Bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values Xi,n on the corresponding inputs. Current sensing circuits are connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents.

公开(公告)号：US10783963B1

公开(公告)日：2020-09-22

申请号：US16297504

申请日：2019-03-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shang-Chi Yang

IPC: G11C13/00 ,  G06N3/063 ,  G06N3/08

Abstract: An in-memory computation device is described that comprises a memory with a plurality of blocks B(n) of cells, where n ranges from 0 to N−1. A page output circuit PO(n) and page input circuit PI(n) are operatively coupled to block B(n) in the plurality of sets. A data bus system for providing an external source of input data and a destination for output data is provided. Data circuits are configurable connect page input circuit PI(n) to one or more of page output circuit PO(n), page output circuit PO(n−1), and the data bus system to source the page input data in a sensing cycle. This configuration can be done between each sensing cycle, or in longer intervals, in order to support a variety of neural network configurations and operations.

公开(公告)号：US10481965B2

公开(公告)日：2019-11-19

申请号：US15389238

申请日：2016-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yih-Shan Yang ,  Shou-Nan Hung ,  Chun-Hsiung Hung ,  Yao-Jen Kuo ,  Meng-Fan Chang

IPC: G06F11/07 ,  G11C16/08 ,  G11C16/34 ,  G06F3/06 ,  G06F11/08 ,  G11C29/00 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C16/26

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

公开(公告)号：US20190206498A1

公开(公告)日：2019-07-04

申请号：US15857940

申请日：2017-12-29

Applicant: Macronix International Co., Ltd.

Inventor： Yiching Liu ,  Chun-Hsiung Hung

IPC: G11C16/22 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/02 ,  G11C16/04

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0255 ,  H01L27/11526 ,  H01L27/11573

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for protecting memory cells from in-process charging effects for a memory system, e.g., NAND flash memory. The methods include: forming a first connection to connect a first node of a diode to a memory cell line coupled with one or more memory cells to be fabricated and a second connection to connect a second node of the diode to a control circuit, such that, during fabricating the memory, in-process charges accumulated on the memory cells are discharged to a ground via a conductive path formed by a first voltage caused by the in-process charges forward biasing the diode and then enabling the control circuit to conduct a current to the ground, and after fabricating the memory and during operating the memory, turning off the conductive path by reverse biasing the diode with a second voltage applied on the control circuit.

公开(公告)号：US10042380B1

公开(公告)日：2018-08-07

申请号：US15427234

申请日：2017-02-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shang-Chi Yang

IPC: G05F3/04 ,  G05F5/00

Abstract: A current flattening circuit, a current compensation circuit and associated control method are provided. The current flattening circuit is electrically connected to a core node, and includes a reference voltage regulator and the current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator. The current compensation circuit generates a compensation current according to a potential difference between the reference voltage and a core voltage corresponding to the core node.