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310 条记录 (耗时 0.045 秒)

    High performance test head and method of making
    131.
    发明授权
    High performance test head and method of making 失效
    高性能测试头和制作方法

    公开(公告)号：US5090118A

    公开(公告)日：1992-02-25

    申请号：US560398

    申请日：1990-07-31

    申请人： On-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi

    发明人： On-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi

    IPC分类号： G01R1/073 ,  G01R31/28 ,  H01R12/04

    CPC分类号： G01R31/2886 ,  G01R1/0735 ,  Y10T29/49149 ,  Y10T29/49155

    摘要： A high performance test head (18) communicates test signals between integrated circuit test pads and integrated circuit tester. Test head (18) comprises metal bumps (22) that electrically couple with test pads to communicate test signals between test pads and test circuitry. Planar foundation plate (30) provides structural support. Compliant material layer (26) associates with metal bumps (22) and compresses to assure positive contact between metal bumps (22) and test pads. Compliant material layer (26) is positioned between foundation plate (30) and metal bumps (22). Interconnection line (20) adjoins test head (18) to connect metal bumps (22) between test circuitry and integrated circuits. The present invention includes a method for high performance communication of test signals between test pads and test circuitry. The present invention further includes the method of applying semiconductor device fabrication techniques to produce a high performance test head (18).

    摘要翻译： 高性能测试头（18）在集成电路测试焊盘和集成电路测试仪之间通信测试信号。 测试头（18）包括与测试焊盘电耦合以在测试焊盘和测试电路之间传送测试信号的金属凸块（22）。 平面基础板（30）提供结构支撑。 合适的材料层（26）与金属凸块（22）相关并且压缩以确保金属凸块（22）和测试垫之间的正接触。 合适的材料层（26）位于基板（30）和金属凸块（22）之间。 互连线（20）邻接测试头（18）以在测试电路和集成电路之间连接金属凸块（22）。 本发明包括用于测试焊盘和测试电路之间的测试信号的高性能通信的方法。 本发明还包括施加半导体器件制造技术以产生高性能测试头（18）的方法。

    Memory device with integrated error detection and correction
    134.
    发明授权
    Memory device with integrated error detection and correction 失效
    具有集成错误检测和校正的存储器件

    公开(公告)号：US4875212A

    公开(公告)日：1989-10-17

    申请号：US310496

    申请日：1989-02-13

    申请人： Masashi Hashimoto

    发明人： Masashi Hashimoto

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/04 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G06F11/1076

    摘要： A semiconductor memory device, comprising an information memory array storing data words each consisting of a predetermined number of information bits, a memory array storing bits generated in accordance with an error detect/correct code, the memory array having bit lines equal in number to the information bits forming each of the data words, the memory array being programmable to create error detection and correction data on the basis of which a bit in error in the main memory array is to be detected and corrected, main sense amplifiers for detecting the information bits read from the main memory array, the main sense amplifiers being equal in number to the information bits forming each of the data words, auxiliary sense amplifiers for detecting an error bit read from the main memory array and output through the main sense amplifiers, the auxiliary sense amplifiers being equal in number to the main sense amplifiers and each producing an error signal in response to an erroneous information bit read from the main memory array through any of the main sense amplifiers, and an error correction circuit intervening between the main and auxiliary sense amplifiers and transparent to an error-free information bit read from the main memory array, the error correction circuit being responsive to the error signal from any of the auxiliary sense amplifiers for inverting the logic state of an erroneous information bit read from the main memory array.

    摘要翻译： 一种半导体存储器件，包括存储每个由预定数量的信息位组成的数据字的信息存储器阵列，存储根据错误检测/正确代码生成的位的存储器阵列，该存储器阵列的位线数量等于 形成每个数据字的信息位，存储器阵列是可编程的，以产生检测和校正主存储器阵列中误差位的误差检测和校正数据;用于检测信息位的主感测放大器 从主存储器阵列读取，主读出放大器的数量与形成每个数据字的信息位相等，辅助读出放大器用于检测从主存储器阵列读取的误差位，并通过主读出放大器输出辅助读出放大器 感测放大器的数量与主感测放大器相等，并且每个产生响应于错误信息的误差信号 通过任何一个主感测放大器从主存储器阵列读取的位读取位和介于主和辅助读出放大器之间的误差校正电路，对从主存储器阵列读取的无错误信息位透明，纠错电路为 响应于来自任何辅助读出放大器的误差信号，用于反转从主存储器阵列读取的错误信息位的逻辑状态。

    Substrate bias generator for dynamic RAM having variable pump current level
    137.
    发明授权
    Substrate bias generator for dynamic RAM having variable pump current level 失效
    用于具有可变泵电流电平的动态RAM的衬底偏置发生器

    公开(公告)号：US4585954A

    公开(公告)日：1986-04-29

    申请号：US512078

    申请日：1983-07-08

    申请人： Masashi Hashimoto ,  Chitranjan Reddy

    发明人： Masashi Hashimoto ,  Chitranjan Reddy

    IPC分类号： G11C11/407 ,  G05F3/20 ,  H03K3/354

    CPC分类号： G05F3/205

    摘要： A dynamic MOS read/write memory has a substrate bias generator circuit which includes, in this example, four separate pump circuits. A first of these operates only during power-up to quickly produce the desired back bias; this pump circuit uses a high frequency oscillator and a low impedence drive, and cuts off to save power as soon as the necessary bias is reached. A second generates a smaller sustaining current, using a lower frequency oscillator and higher impedance drive; this functions to compensate for leakage during idle periods. The third and fourth pump circuits are driven by RAS and CAS, so these occur only when needed, and at a rate dependent upon the actual operating condition of the memory.

    摘要翻译： 动态MOS读/写存储器具有衬底偏置发生器电路，在该示例中包括四个单独的泵电路。 其中的第一个仅在加电期间操作以快速产生期望的背偏压; 该泵电路使用高频振荡器和低阻抗驱动器，并且一旦达到必要的偏置就切断电源。 第二个产生较小的维持电流，使用较低频率的振荡器和较高的阻抗驱动; 这样做可以补偿空闲期间的泄漏。 第三和第四个泵电路由＆upbar＆R和＆amp; upbar＆C驱动，因此这些仅在需要时发生，并且速率取决于存储器的实际操作条件。

    Azetidinone compounds and processes for preparation thereof
    138.
    发明授权
    Azetidinone compounds and processes for preparation thereof 失效
    氮杂环丁酮化合物及其制备方法

    公开(公告)号：US4576753A

    公开(公告)日：1986-03-18

    申请号：US629216

    申请日：1984-07-09

    申请人： Takashi Kamiya ,  Masashi Hashimoto ,  Osamu Nakaguti

    发明人： Takashi Kamiya ,  Masashi Hashimoto ,  Osamu Nakaguti

    IPC分类号： C07C323/25 ,  C07D205/08 ,  C07D205/085 ,  C07D205/095 ,  C07D251/04 ,  A61K31/42 ,  C07D403/04 ,  C07D409/06

    CPC分类号： C07C323/25 ,  C07D205/08 ,  C07D205/085 ,  C07D205/095 ,  C07D251/04

    摘要： This invention relates to new 2-azetidinone compounds, which have antimicrobial activities, and to processes for the preparation thereof, and more particularly, this invention provides new 2-azetidinone compounds, especially ones having various substituted carboxyalkyl radicals at the first position and having various groups at the fourth position of the azetidinone nucleus, which have antimicrobial activities against various pathogenic microorganisms and are useful as antibiotics in treatment for microbial infections in mammals including human beings and animals.

    摘要翻译： 本发明涉及具有抗菌活性的新的2-氮杂环丁酮化合物及其制备方法，更具体地说，本发明提供新的2-氮杂环丁酮化合物，特别是在第一位置具有各种取代的羧基烷基的化合物， 在氮杂环丁酮核的第四位置的基团，其具有针对各种致病微生物的抗微生物活性，并且可用作治疗哺乳动物（包括人和动物）中的微生物感染的抗生素。