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267 条记录 (耗时 0.029 秒)

    Photonic device package with aligned lens cap
    131.
    发明授权
    Photonic device package with aligned lens cap 有权
    带有对准镜头盖的光子器件封装

    公开(公告)号：US07456945B2

    公开(公告)日：2008-11-25

    申请号：US10693795

    申请日：2003-10-24

    申请人： Robert Shih ,  Chun Lei ,  John Chen

    发明人： Robert Shih ,  Chun Lei ,  John Chen

    IPC分类号： G01B11/26

    CPC分类号： H01L31/0203 ,  G02B6/4206 ,  H01S5/02212 ,  H01S5/02288

    摘要： A photonic device package with a passively aligned lens cap is disclosed. The lens cap is positioned with an unobstructed view of the lens portion of the lens cap. A header holding a photonic device, is moved relative to the cap or vice versa until the video display system indicates that the photonic device is aligned to the lens. The cap is held in alignment by forming at least one weld point between the cap and the header. A subsequent hermetic sealing process can be used to permanently seal the cap to the header.

    摘要翻译： 公开了一种具有被动对准的透镜盖的光子器件封装。 透镜盖定位成透镜盖的透镜部分的无阻挡视图。 保持光子器件的头部相对于盖子移动，反之亦然，直到视频显示系统指示光子器件与透镜对准。 通过在盖和集管之间形成至少一个焊接点来将盖保持对准。 随后的气密密封过程可用于将盖永久地密封到集管。

    Fruit container
    133.
    外观设计
    Fruit container 有权
    水果容器

    公开(公告)号：USD573015S1

    公开(公告)日：2008-07-15

    申请号：US29286158

    申请日：2007-04-25

    申请人： John Chen

    设计人： John Chen

    QOS-BASED MULTI-PROTOCOL UPLINK ACCESS
    137.
    发明申请
    QOS-BASED MULTI-PROTOCOL UPLINK ACCESS 有权
    基于QOS的多协议上行链路访问

    公开(公告)号：US20070147326A1

    公开(公告)日：2007-06-28

    申请号：US11610161

    申请日：2006-12-13

    申请人： John Chen

    发明人： John Chen

    IPC分类号： H04Q7/24

    CPC分类号： H04W74/002 ,  H04W48/12 ,  H04W74/0833 ,  H04W74/0866

    摘要： A method and apparatus for multi-protocol uplink access defines two protocols and maps each to one of a user's access service class (ASC) and quality of service (QoS). A first uplink access protocol type is defined in which a random access channel (RACH) burst is sent and an acquisition indicator channel (AICH) burst is sent, and a channel assignment grant is sent on another downlink channel. A second uplink access protocol type is defined in which a RACH preamble is sent and an AICH burst is sent.

    摘要翻译： 用于多协议上行链路接入的方法和装置定义了两个协议并且将每个协议映射到用户的接入服务类别（ASC）和服务质量（QoS）中的一个。 定义了第一上行链路接入协议类型，其中发送随机接入信道（RACH）突发并且发送采集指示符信道（AICH）突发，并且在另一个下行链路信道上发送信道分配许可。 定义了第二上行链路接入协议类型，其中发送RACH前导码并发送AICH突发。

    Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies
    138.
    发明申请
    Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies 审中-公开
    应变诱导的移动性增强纳米器件结构和CMOS技术的集成工艺架构

    公开(公告)号：US20070072376A1

    公开(公告)日：2007-03-29

    申请号：US11244955

    申请日：2005-10-05

    申请人： John Chen ,  Simon Yang

    发明人： John Chen ,  Simon Yang

    IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/77 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.

    摘要翻译： CMOS半导体集成电路器件。 CMOS器件包括NMOS器件，其包括栅极区域，源极区域和漏极区域以及形成在源极区域和漏极区域之间的NMOS沟道区域。 在源极区域内形成碳化硅材料并形成在漏极区域内。 碳化硅材料使得沟道区域处于拉伸模式。 CMOS器件还具有包括栅极区域，源极区域和漏极区域的PMOS器件。 PMOS器件具有形成在源极区域和漏极区域之间的PMOS沟道区域。 源极区内形成硅锗材料，并形成在漏区。 硅锗材料使沟道区域处于压缩模式。

    Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors
    139.
    发明申请
    Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors 有权
    使用用于应变硅MOS晶体管的栅极图案化的纯二氧化硅硬掩模的方法和结构

    公开(公告)号：US20070063221A1

    公开(公告)日：2007-03-22

    申请号：US11245412

    申请日：2005-10-05

    申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian Ning

    发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian Ning

    IPC分类号： H01L31/00

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

    摘要： A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.

    摘要翻译： 部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻的源极区域和蚀刻的漏极区域中具有外延生长的填充材料（例如，硅/锗，碳化硅）。 优选地，蚀刻的源极区域和蚀刻的漏极区域耦合到栅极结构。 该装置在填充的源区和填充的漏极区之间具有至少从形成在蚀刻的源极区和蚀刻的漏极区中的填充材料的应变通道区。