公开(公告)号：US20080050878A1

公开(公告)日：2008-02-28

申请号：US11529502

申请日：2006-09-29

Applicant: Jung Wu Chien ,  Chia Shun Hsiao

Inventor： Jung Wu Chien ,  Chia Shun Hsiao

IPC: H01L21/8236

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Abstract translation: 一种用于制备存储器结构的方法包括以下步骤：在衬底的电介质结构上形成多个线状块，并形成露出线状块的侧壁的第一蚀刻掩模。 除去包含第一蚀刻掩模的线状块的一部分以减小线状块的宽度，以形成包括以隔行方式布置的多个第一块和第二块的第二蚀刻掩模。 随后，去除未被第二蚀刻掩模覆盖的介电结构的一部分，以在电介质结构中形成多个开口，并且在每个开口中形成导电插塞。 多个开口包括位于第一块之间的第一开口和位于第二块之间的第二开口，并且第一开口和第二开口延伸到有源区域的相对侧。

公开(公告)号：US20080042243A1

公开(公告)日：2008-02-21

申请号：US11561365

申请日：2006-11-17

Applicant: Hengyuan Lee ,  Der-Sheng Chao

Inventor： Hengyuan Lee ,  Der-Sheng Chao

IPC: H01L29/12

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: Phase change memory devices and methods for fabricating the same. An exemplary phase change memory device comprises a conductive element formed in a dielectric layer. A phase change material layer is formed in the dielectric layer. A conductive layer extends in the dielectric layer to respectively electrically connect the phase change layer and a sidewall of the conductive element.

Abstract translation: 相变存储器件及其制造方法。 示例性相变存储器件包括形成在电介质层中的导电元件。 在电介质层中形成相变材料层。 导电层在电介质层中延伸，以分别电连接相变层和导电元件的侧壁。

公开(公告)号：US07319058B2

公开(公告)日：2008-01-15

申请号：US11161724

申请日：2005-08-15

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract translation: 提供了一种用于非易失性存储器的制造方法。 为了制造非易失性存储器，在衬底中形成多个第一沟槽和第二沟槽，其中第二沟槽设置在第一沟槽上方并跨过第一沟槽。 然后，在每个第二沟槽的两个侧壁上依次形成隧穿层和电荷存储层。 隔离层被填充到第一沟槽中。 此外，在第二沟槽的侧壁上形成电荷阻挡层，在第二沟槽的底部形成栅极电介质层。 控制栅极层被填充到第二沟槽中。 最后，在控制栅极层两侧的衬底中形成两个第一掺杂区。

公开(公告)号：US20070298547A1

公开(公告)日：2007-12-27

申请号：US11510937

申请日：2006-08-28

Applicant: Po-Kang Hu ,  Ta-Wei Tung

Inventor： Po-Kang Hu ,  Ta-Wei Tung

IPC: H01L21/82 ,  H01L21/326 ,  H01L21/44

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device comprises a fuse bank with a fuse window, a pad area with a pad window, and a composite passivation layer comprising a sacrificial dielectric layer and a final passivation layer. Both the fuse window and the pad window have a bottom portion and two sidewalls, and the composite passivation layer covers both the fuse bank and the pad area except for the bottom portions of the fuse bank and the pad area.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括具有熔丝窗口的熔丝组，具有焊盘窗口的焊盘区域以及包括牺牲绝缘层和最终钝化层的复合钝化层。 熔丝窗口和焊盘窗口都具有底部和两个侧壁，并且复合钝化层覆盖熔丝排和焊盘区域，除了保险丝组的底部和焊盘区域之外。

公开(公告)号：US20070285962A1

公开(公告)日：2007-12-13

申请号：US11741717

申请日：2007-04-27

Applicant: Chuo Yen ,  Ming-Hau Tseng

Inventor： Chuo Yen ,  Ming-Hau Tseng

IPC: G11C11/00 ,  H01L21/76

CPC classification number: H01L45/144 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675

Abstract: A phase change memory device is disclosed. A first columnar electrode and a second columnar electrode are provided, both arranged horizontally. A phase change layer is interposed between the first columnar electrode and the second columnar electrode, electrically connecting both thereof, wherein the entirety of the phase change layer is disposed on a plane. A bottom electrode electrically connects the first columnar electrode. A top electrode electrically connects the second columnar electrode.

Abstract translation: 公开了一种相变存储器件。 设置有水平排列的第一柱状电极和第二柱状电极。 相变层插入在第一柱状电极和第二柱状电极之间，将其两者电连接，其中整个相变层设置在平面上。 底部电极电连接第一柱状电极。 顶部电极电连接第二柱状电极。

公开(公告)号：US20070272962A1

公开(公告)日：2007-11-29

申请号：US11465881

申请日：2006-08-21

Applicant: Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: H01L29/94 ,  H01L21/336 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract translation: 提供具有L形间隔物的半导体器件及其制造方法。 半导体器件包括衬底，复合间隔物和隧道绝缘层。 衬底包括浅沟槽隔离结构和相邻有源区。 复合间隔物形成在浅沟槽隔离结构的侧壁上，还包括第一绝缘层和L形第二绝缘层间隔物，其中第一绝缘层位于L形第二绝缘层间隔物和 基质。 隧道绝缘层位于有源区的衬底上，并与其相应侧上的复合衬垫的第一绝缘层相连。

公开(公告)号：US07301196B2

公开(公告)日：2007-11-27

申请号：US11112702

申请日：2005-04-22

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160). A dielectric layer (1510) overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate (140). The control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在非易失性存储器中，在半导体衬底（120）中形成衬底隔离区（220）。 衬底隔离区域是突出于衬底上方的电介质区域。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区被暴露，并且浮选层从至少一部分选择栅极线上去除。 在浮动栅极层上形成电介质（1510），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些突起被利用来独立于光刻对准来限定控制栅。 然后，浮动栅极独立于除图案化衬底隔离区域和选择栅极线之外的对准的任何光刻对准。 在另一方面，非易失性存储单元具有导电浮动栅极（160）。 覆盖浮置栅极的介电层（1510）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的连续特征。 控制栅极（160）覆盖在电介质层的连续特征上，并且覆盖在浮动栅极而不是选择栅极。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US07297628B2

公开(公告)日：2007-11-20

申请号：US10718320

申请日：2003-11-19

Applicant: Chunyuan Chao ,  Kuei-Chang Tsai ,  George A. Kovall

Inventor： Chunyuan Chao ,  Kuei-Chang Tsai ,  George A. Kovall

IPC: H01L21/4763

CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/76816

Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Abstract translation: 在设置在图案化光致抗蚀剂层下方的防反射涂层（ARC层）中产生向内锥形的开口。 向内锥形开口的较小的底部宽度尺寸用于限定在ARC层下方设置的层间介质区域（ILD）中的另外的开口。 在一个实施例中，ILD将集成电路的有源层集合与其第一主互连层分开。 此外，在一个实施例中，锥形诱导蚀刻配方用于产生向内锥形的ARC开口，其中蚀刻配方使用CF4和CHF3的混合物，其中CF4 / CHF3体积流入比基本上小于5:1， 更优选更接近1比1。

公开(公告)号：US07297597B2

公开(公告)日：2007-11-20

申请号：US10898273

申请日：2004-07-23

Applicant: Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

Inventor： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

Abstract: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height. Additionally, adjacent low and high voltage transistors may benefit from simultaneous formation of their gate dielectrics with use of the radical-based oxidizing method.

Abstract translation: ONO型记忆体堆叠中的顶层氧化物的常规制造通常产生Bird's Beak。 叠层中的某些材料如氮化硅相对难以氧化。 因此，氧化不会沿着ONO型堆叠的多层高度均匀地进行。 本公开显示了如何基于根基的ONO堆叠的顶部氧化物的制造（即通过ISSG方法）可以帮助减少Bird's Beak的形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料，例如氮化硅，并且表明短寿命氧化剂交替地或另外不会扩散深 通过已经氧化的ONO堆叠层，例如较低的氧化硅层。 结果，可以制造更均匀的顶部氧化物电介质，沿其高度具有更均匀的击穿电压。 此外，相邻的低压和高压晶体管可以受益于使用基于自由基的氧化方法同时形成其栅极电介质。

公开(公告)号：US20070254218A1

公开(公告)日：2007-11-01

申请号：US11449658

申请日：2006-06-09

Applicant: Yee Kai Lai

Inventor： Yee Kai Lai

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/34 ,  G03F1/36

Abstract: A phase shifting mask capable of decreasing the optical proximity effect comprises a substrate and at least one phase shifting pattern positioned on the substrate, wherein the phase shifting pattern surrounds at least one optical correction pattern. Preferably, the optical correction pattern is an aperture exposing the substrate, and positioned on an intersection or a corner of the phase shifting pattern. The method for preparing the phase shifting mask comprises steps of forming a polymer layer on a substrate, illuminating a first predetermined region of the polymer layer by an electron beam to change the molecular structure of the polymer layer in the first predetermined region, which surrounds at least one second predetermined region. Subsequently, the polymer layer outside the first predetermined region is removed to form a phase shifting pattern, while the second predetermined region forms an optical correction pattern.

Abstract translation: 能够减小光学邻近效应的相移掩模包括衬底和位于衬底上的至少一个相移图案，其中相移图案包围至少一个光学校正图案。 优选地，光学校正图案是暴露衬底并定位在相移图案的交叉点或拐角上的孔。 制备相移掩模的方法包括以下步骤：在基底上形成聚合物层，通过电子束照射聚合物层的第一预定区域，以改变聚合物层在第一预定区域内的分子结构， 至少一秒预定区域。 随后，除去第一预定区域外的聚合物层以形成相移图案，而第二预定区域形成光学校正图案。