公开(公告)号：US20140156248A1

公开(公告)日：2014-06-05

申请号：US14084727

申请日：2013-11-20

Applicant: STMICROELECTRONICS SA

Inventor： JEAN-ROBERT MANOUVRIER

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G09B23/18

Abstract: A simulation method for a P-I-N junction photodiode uses a model that may include a diode model configured to characterize electrical behavior of the P-I-N junction photodiode, and an input for applying a fictitious electrical signal representing optical power received by the P-I-N junction photodiode. A current source model may be coupled to the diode model and may have a transient response to a variation of the fictitious electrical signal, based upon a sum of a first first-order transient response with a time constant based upon to a transit time of carriers in a depletion region of the P-I-N junction, and a second first-order transient response with a time constant based upon a diffusion time of carriers outside of the depletion region. The first and second responses may be respectively weighted by a length of the depletion region and a length of the P-I-N junction outside the depletion region.

Abstract translation: 用于P-I-N结光电二极管的模拟方法使用可以包括被配置为表征P-I-N结光电二极管的电气行为的二极管模型的模型，以及用于施加表示由P-I-N结光电二极管接收的光功率的虚拟电信号的输入。 电流源模型可以耦合到二极管模型，并且可以基于第一一阶瞬态响应与基于载波的传输时间的时间常数的和来对虚拟电信号的变化进行瞬态响应 在PIN结的耗尽区和基于耗尽区外的载流子的扩散时间的时间常数的第二一阶瞬态响应。 第一和第二响应可以分别由耗尽区的长度和耗尽区之外的P-I-N结的长度加权。

公开(公告)号：US08730756B2

公开(公告)日：2014-05-20

申请号：US13312679

申请日：2011-12-06

Applicant: Nishu Kohli ,  Robin M. Wilson

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘而可操作的存储器组件; 以及响应于系统时钟产生内部时钟的内部时钟产生电路，其中响应于系统时钟的上升沿和下降沿产生内部时钟的第一边缘。

公开(公告)号：US08712466B2

公开(公告)日：2014-04-29

申请号：US13302891

申请日：2011-11-22

Applicant: Baudouin Martineau ,  Olivier Richard ,  Frédéric Gianesello

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frédéric Gianesello

IPC: H04M1/00

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract translation: 一种由1到2个分离器形成的多通道分离器，其中：第一个1到2个分离器的输入端限定了多通道分离器的输入; 1〜2个分离器电串联连接; 并且1至2个分配器的第一相应输出定义多通道分离器的输出端子。

公开(公告)号：US20140075726A1

公开(公告)日：2014-03-20

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。

公开(公告)号：US20140015002A1

公开(公告)日：2014-01-16

申请号：US13921436

申请日：2013-06-19

Applicant: STMicroelectronics SA

Inventor： Pascal FONTENEAU

IPC: H01L29/749

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/1203 ,  H01L27/1207

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated there-from by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract translation: 保护在被布置在绝缘层本身上的SOI型半导体层中形成的过电压的MOS晶体管，其本身布置在半导体衬底上，该半导体衬底包括至少部分地在MOS晶体管下方形成在衬底中的横向场效应控制晶闸管，场效应转 在所述晶体管的至少一部分在所述MOS晶体管的主电极的至少一部分延伸的区域之外，所述晶闸管的所述绝缘层，所述晶闸管的阳极和阴极分别连接到所述漏极和源极 MOS晶体管，从而在MOS晶体管的漏极和源极之间的正过电压的情况下晶闸管导通。

公开(公告)号：US20130321057A1

公开(公告)日：2013-12-05

申请号：US13904606

申请日：2013-05-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Dimitri Soussan ,  Sylvain Majcherczak ,  Alexandre Valentian ,  Marc Belleville

IPC: H03K19/0185

CPC classification number: H03K19/018578 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract translation: 集成电路可以包括包括包括MOSFET晶体管的子组件的缓冲级的数字输出端口。 一个子组件可以包括具有连接到公共高电压的源的两个上拉晶体管，并且具有连接到连接到输出端子的公共节点的漏极。 另一个子组件可以包括具有连接到公共低电压的源的下拉晶体管，并且具有连接到公共节点的漏极。 上拉和下拉晶体管形成在FDSOI衬底的薄半导体层中。 衬底可以包括厚半导体层和分离薄和厚半导体层的氧化物层。 面向上拉和下拉晶体管的厚半导体层的区域可以连接到被配置为改变上拉和下拉晶体管的阈值电压的电路。

公开(公告)号：US08598938B2

公开(公告)日：2013-12-03

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/687

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。

公开(公告)号：US08594226B2

公开(公告)日：2013-11-26

申请号：US12522011

申请日：2008-01-10

Applicant: Andreia Cathelin ,  Antoine Frappe ,  Andreas Kaiser

Inventor： Andreia Cathelin ,  Antoine Frappe ,  Andreas Kaiser

IPC: H04L27/04 ,  H04L27/20

CPC classification number: H03M7/304 ,  H03M7/3026

Abstract: The digital delta-sigma modulator includes a signal input for receiving digital samples of N bits, and a digital filter connected to the signal input. The digital filter performs addition/subtraction and integration operations according to a redundant arithmetic coding for delivering digital filtered samples. A quantizer performs a nonexact quantization operation so as to deliver digital output samples of n bits, with n being less than N. The input of the quantizer is connected within the digital filter.

Abstract translation: 数字delta-sigma调制器包括用于接收N位数字采样的信号输入端和连接到信号输入端的数字滤波器。 数字滤波器根据用于传送数字滤波样本的冗余算术编码执行加法/减法和积分操作。 量化器执行非事件量化操作，以便在n小于N的情况下传送n位的数字输出采样。量化器的输入连接在数字滤波器内。

公开(公告)号：US08572468B2

公开(公告)日：2013-10-29

申请号：US12754845

申请日：2010-04-06

Applicant: David Furodet

Inventor： David Furodet

IPC: H03M13/00

CPC classification number: H03M13/09 ,  H03M13/033 ,  H03M13/036 ,  H03M13/17

Abstract: A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 2s-1-3 consecutive erroneous bits.

Abstract translation: 一种方法是用于发送在r比特上编码的二进制信息字（MI），附加了以s位编码的冗余（CRC），s和r为整数。 冗余（CRC）在发送之后发出错误比特的出现，并且通过执行由最多s比特编码的生成多项式来发送的信息字（MI）的欧几里德除法获得。 选择生成多项式使得其满足以下条件中的至少一个，即生成多项式的倍数的汉明权重大于或等于所选择的阈值，或者生成多项式允许检测至少2s -1-3个连续的错误位。

公开(公告)号：US20130264677A1

公开(公告)日：2013-10-10

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe GALY ,  Jean JIMENEZ

IPC: H01L27/02 ,  H01L21/77

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。