Abstract:
A ramp signal generation circuit 21 comprises a plurality of unit circuits 221 to 22N, each including a capacitor 26 having one end 26a held at a fixed potential and a current source 27 connected to the other end 26b of the capacitor 26, while the other ends 26b of the capacitors 26 in the plurality of unit circuits 221 to 22N are connected to each other with a wiring member W.
Abstract:
A radiation imaging apparatus including pixels; driving lines; a driving circuit; bias lines; an acquisition unit configured to acquire an evaluation value based on a current flowing in the bias line; a determination unit configured to compare the evaluation value with a comparison target value to determine whether radiation is irradiated; a control unit configured to control the acquisition unit and the determination unit; and a storage unit configured to store the evaluation value used in the determination process, is provided. A comparison target value used in a given determination process is based on one or more evaluation values used in one or more determination processes which are performed before the given determination process and in which it is determined that radiation has not been irradiated.
Abstract:
A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.
Abstract:
A solid-state imaging device includes a pixel array, control lines TG each provided for a corresponding one of rows of pixels and configured to control, e.g., operation of a transfer transistor, and a driver circuit 103 configured to control the operation of the transfer transistor through the control lines TG and connected to a power-supply line TGL. The solid-state imaging device performs all reset operation for resetting signal charges of all pixels by the driver circuit 103 and reading operation for reading a pixel signal from each row of the pixels. An impedance controller 130 configured to control an impedance value for power-supply line TGL in the reading operation to be less than an impedance value for power-supply line TGL in the all reset operation is provided.
Abstract:
A semiconductor apparatus, comprising a decoder arranged in a path between a first power supply line and a second power supply line and configured to receive a signal and decode the signal, a switch portion arranged, in series with the decoder, in the path between the first power supply line and the second power supply line, and a control unit configured to set the switch portion in a conductive state so as to cause the decoder to decode the signal after the signal has changed from one of high level and low level to the other.
Abstract:
An output impedance of a drive unit configured to drive a drive line is set to be varied during a period in which a drive pulse for setting each transfer transistor to be in a conductive state is supplied and during a period in which a drive pulse for setting each transfer transistor to be in a non-conductive state is supplied.
Abstract:
A driver includes a first level shifting unit generating a second signal swinging in a second threshold range in response to a first signal swinging in a first threshold range, a second level shifting unit generating a third signal swinging in a third threshold range in response to the second signal, a first pull-up driving unit driving an output terminal with a first high-voltage in response to the second signal, a first pull-down driving unit driving the output terminal with a first low voltage in response to the third signal, a second pull-down driving unit driving the output terminal with a second low voltage higher than the first low voltage in response to the fourth signal, and a first path coupling unit coupling the second pull-down driving unit with the output terminal in response to the second signal.
Abstract:
An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.
Abstract:
The present invention relates to an image sensor capable of obtaining a good-quality image with a simple configuration.A pixel accumulates a charge by performing photoelectric conversion on incident light, and outputs a pixel signal corresponding to the charge. A vertical scanning circuit controls the pixel to cause the pixel to perform a shutter process of discharging an unnecessary charge accumulated in the pixel, a charge accumulation process of accumulating a charge generated through photoelectric conversion in a predetermined exposure time in the pixel, and a read process of outputting a pixel signal corresponding to the charge accumulated in the pixel in the charge accumulation process. Also, the control means causes the charge generated through photoelectric conversion in the pixel to be discharged in a non-accumulation period, which is a period other than a period when the shutter process is being performed, a period when the charge accumulation process is being performed, and a period when the read process is being performed. The present invention can be applied to a CMOS sensor, for example.
Abstract:
A camera array, an imaging device and/or a method for capturing image that employ a plurality of imagers fabricated on a substrate is provided. Each imager includes a plurality of pixels. The plurality of imagers include a first imager having a first imaging characteristics and a second imager having a second imaging characteristics. The images generated by the plurality of imagers are processed to obtain an enhanced image compared to images captured by the imagers. Each imager may be associated with an optical element fabricated using a wafer level optics (WLO) technology.