公开(公告)号：US07625666B2

公开(公告)日：2009-12-01

申请号：US11905282

申请日：2007-09-28

Applicant: Tomoyuki Shose ,  Katsuyuki Kida ,  Masao Kondou ,  Yasuo Akai

Inventor： Tomoyuki Shose ,  Katsuyuki Kida ,  Masao Kondou ,  Yasuo Akai

IPC: H01M2/02

CPC classification number: H01M2/0413 ,  H01M2/0222 ,  H01M10/052 ,  H05K3/341 ,  H05K2201/0373 ,  H05K2201/10462 ,  H05K2201/10643 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10S228/901

Abstract: A lead plate-attached coin-type battery is constituted from a combination of a coin-type battery and a positive lead plate. In the coin-type battery, a negative cap seals the aperture of a positive outer can. In a lateral view, the positive lead plate is crank-shaped, and one end thereof is attached to the outer surface of the positive outer can of the coin-type battery. A lead plate is not attached to the negative cap. One or more projections that project in the Z axis direction are provided on the negative cap. In the lead plate-attached coin-type battery, the positive lead plate and negative cap have been attached to respective conductive lands on a circuit board by a solder reflow method.

Abstract translation: 引线板式硬币型电池由硬币型电池和正极引线板的组合构成。 在硬币型电池中，负极帽密封正外壳的孔径。 在侧视图中，正极引线板是曲柄形的，其一端连接到硬币型电池的正外壳的外表面。 引线板未连接到负极盖。 在Z轴方向上投影的一个或多个突起设置在负极盖上。 在带引线板的硬币型电池中，通过焊料回流法将正极引线板和负极盖安装在电路板上的各个导电焊盘上。

公开(公告)号：US20090250506A1

公开(公告)日：2009-10-08

申请号：US12379524

申请日：2009-02-24

Applicant: Deepak K. Pai

Inventor： Deepak K. Pai

IPC: B23K1/20

CPC classification number: H05K3/341 ,  H01L23/4822 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface.

Abstract translation: 提供了一种用于制备用于连接到表面的集成电路的方法，所述集成电路包括引线触点和无引线触点。 该方法包括提供集成电路，将第一焊膏施加到无引线触点，在所施加的焊膏上形成焊球，加热焊球，从而去除至少一部分第一焊膏并使焊球进入电 与无引线触点接触，焊球的基部通常在平面中对准，并且将引线触点弯曲成鸥翼，鸥翼的基部与平面基本上共面。 鸥翼的基部和至少一个焊球的基部通常限定接触平面，以便将来与表面接触。

公开(公告)号：US20090196002A1

公开(公告)日：2009-08-06

申请号：US12362149

申请日：2009-01-29

Applicant: Kenji FUKUZONO

Inventor： Kenji FUKUZONO

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H05K3/0058 ,  H05K3/301 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/0311 ,  H05K2201/10659 ,  H05K2201/10734 ,  H05K2201/2009 ,  H05K2201/2018

Abstract: A printed wiring board unit includes an electronic circuit component, a printed wiring board, a plurality of first conductive terminals disposed between the electronic circuit component and the printed wiring board, at least one of the first conductive terminals arranged along a quadrangular outline, and a plurality of second conductive terminals disposed between the electronic circuit component and the printed wiring board, the second conductive terminals arranged at a corner of the quadrangular outline, and the second conductive terminals contacting at least one of the printed wiring board and the electronic circuit component in a relatively displaceable manner.

Abstract translation: 印刷电路板单元包括电子电路部件，印刷线路板，布置在电子电路部件和印刷线路板之间的多个第一导电端子，沿着四边形轮廓布置的至少一个第一导电端子，以及 设置在电子电路部件和印刷线路板之间的多个第二导电端子，布置在四边形轮廓的角部的第二导电端子和与印刷线路板和电子电路部件中的至少一个接触的第二导电端子 相对位移的方式。

公开(公告)号：US20080283982A1

公开(公告)日：2008-11-20

申请号：US12152802

申请日：2008-05-15

Applicant: Chung-Lun Liu ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chang-Yueh Chan ,  Chih-Ming Huang

Inventor： Chung-Lun Liu ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chang-Yueh Chan ,  Chih-Ming Huang

IPC: H01L21/58 ,  H01L23/495

CPC classification number: H05K1/141 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/1034 ,  H05K2201/10659 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads. By the multi-chip semiconductor device and the method for fabricating the same as proposed in the present invention, problems like poor reliability caused by stress induced by several types of materials in a semiconductor package into which a substrate and leads are integrated, moisture absorption by an encapsulated substrate, and cracks developed as a result of moisture absorption by the substrate can be avoided.

Abstract translation: 本发明提出一种具有引线的多芯片半导体器件及其制造方法。 该方法包括以下步骤：提供具有设置在其表面上的多个连接焊盘的基板; 将多个半导体芯片安装在所述基板的表面上，并且将所述半导体芯片电连接到所述基板的表面; 在衬底上形成密封剂以封装半导体芯片并暴露连接焊盘以形成封装单元; 并且提供具有多个引线的引线框架，并且将从封装单元暴露的连接焊盘电连接到引线框架的引线以形成具有引线的多芯片半导体器件，从而形成具有引线的多芯片半导体器件 。 通过本发明中提出的多芯片半导体器件及其制造方法，由半导体封装中由几种材料引起的应力引起的可靠性差的问题，其中衬底和引线被集成到其中，由于 可以避免被封装的基材和由于基材吸湿而显影的裂纹。

公开(公告)号：US20080151512A1

公开(公告)日：2008-06-26

申请号：US11615484

申请日：2006-12-22

Applicant: Kenneth W. Johnson

Inventor： Kenneth W. Johnson

IPC: H05K5/02

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/09781 ,  H05K2201/10659 ,  Y02P70/613 ,  H01L2924/00

Abstract: An integrated circuit substrate has an array of surface interconnects and corner features with attachment elements. The corner features extend past the generally rectilinear perimeter of the substrate providing a lever arm to enhance the strength of the attachment elements thereby protecting the integrity of the array of surface interconnects.

Abstract translation: 集成电路基板具有表面互连阵列和具有附接元件的拐角特征。 角部特征延伸超过基板的大致直线的周边，提供杠杆臂以增强附接元件的强度，从而保护表面互连阵列的完整性。

公开(公告)号：US20080038943A1

公开(公告)日：2008-02-14

申请号：US11629852

申请日：2005-05-24

Applicant: Tatsuya Hayakawa ,  Tatsuya Oka

Inventor： Tatsuya Hayakawa ,  Tatsuya Oka

IPC: H01R12/02

CPC classification number: H05K7/026 ,  H01R9/2425 ,  H01R9/2466 ,  H05K1/144 ,  H05K3/3447 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10659

Abstract: Three printed boards are stored in a case, and a relay connector for connecting the three printed boards is mounted on the second printed board at the middle position. The relay connector is provided with a first terminal storing part, which is long in a vertical direction, and a short second terminal storing part. The relay connector connects a terminal pin of the first printed board at an upper position with a terminal pin of the third printed board at a lower position, via a long first relay terminal stored in the first terminal storing part, while connecting a terminal pin of the first printed board and/or the terminal pin of the third printed board with a conductor of the second printed board, via a short second relay terminal stored in the second terminal storing part.

Abstract translation: 三个印刷电路板被存放在壳体中，并且用于连接三个印刷电路板的中继连接器安装在中间位置的第二印刷电路板上。 中继连接器设置有在垂直方向上长的第一端子存储部和短的第二端子存储部。 继电器连接器通过存储在第一端子存储部分中的长的第一中继端子将位于第一印刷电路板的上部位置的端子销与第三印刷电路板的端子引脚连接在下部位置，同时连接 通过存储在第二终端存储部分中的短的第二中继终端，具有第二印刷电路板的导体的第三印刷电路板的第一印刷电路板和/或端子销。

公开(公告)号：US20070290341A1

公开(公告)日：2007-12-20

申请号：US11762604

申请日：2007-06-13

Applicant: Chang-Young PARK

Inventor： Chang-Young PARK

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/3415 ,  H01L22/34 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A semiconductor package having a good joint to an external board, providing easy measurement control of the electrical characteristics of a semiconductor chip, and ensuring a sufficient number of input and output terminals, and a method of mounting the same are provided. The semiconductor package comprises a plurality of connection terminals aligned individually, and a plurality of conductive wires spaced from the connection terminals. The connection terminals and the wires are bonded to one side of a body, and an interconnection connecting at least one pair of the connection terminal and the wire is formed in the body.

Abstract translation: 具有与外部板接合良好的半导体封装，提供对半导体芯片的电气特性的容易的测量控制以及确保足够数量的输入和输出端子及其安装方法。 半导体封装包括单独排列的多个连接端子和与连接端子间隔开的多个导线。 连接端子和电线被接合到主体的一侧，并且在主体中形成连接至少一对连接端子和电线的互连。

公开(公告)号：US07249411B2

公开(公告)日：2007-07-31

申请号：US10885400

申请日：2004-07-06

Applicant: Yakov Belopolsky

Inventor： Yakov Belopolsky

IPC: H05K3/30

CPC classification number: H05K3/3415 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K3/244 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/3463 ,  H05K2201/09781 ,  H05K2201/10659 ,  H05K2201/10734 ,  H05K2203/047 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49222 ,  H01L2224/0401

Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.

Abstract translation: 描述了将电气部件安装在基板上并可靠地保持部件的方法。 所述方法包括在回流过程期间改变介于组分保持性针和保持性通孔之间的焊膏组合物。 还描述了包括电路板和安装在其上的电气部件的电子组件。 在电子组装实施例之一中，最初与安装的电气部件相关联的材料迁移到将电气部件连接到电路板的焊膏中。

公开(公告)号：US20070002551A1

公开(公告)日：2007-01-04

申请号：US11308052

申请日：2006-03-04

Applicant: CHIH-CHAN (Clay) GER

Inventor： CHIH-CHAN (Clay) GER

IPC: H05K1/11

CPC classification number: H05K1/141 ,  H01L2224/48091 ,  H01L2224/73257 ,  H05K1/0218 ,  H05K3/3442 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10287 ,  H05K2201/10659 ,  H01L2924/00014

Abstract: A printed circuit board (PCB) assembly includes a first PCB (100) and a second PCB (200), respectively including first conductor trace lines (102) and second conductor trace lines (108) for providing electronic connections among a plurality of electronic components. The first PCB is disposed above the second PCB, and is parallel with the second PCB. The first PCB is electronically connected to the second PCB via at least one of the first conductor trace lines and the second conductor trace lines. A surface area of the first PCB is smaller than that of the second PCB. The second PCB is used as a primary circuit board for a layout of electronic components. Preferably, complex or high voltage circuits are disposed on the first PCB, and other circuits are disposed on the second PCB.

Abstract translation: 印刷电路板（PCB）组件包括第一PCB（100）和第二PCB（200），第一PCB（100）和第二PCB（200）分别包括第一导体迹线（102）和第二导体迹线（108），用于在多个电子部件 。 第一PCB设置在第二PCB上方，并与第二PCB平行。 第一PCB通过第一导体迹线和第二导体迹线中的至少一个电连接到第二PCB。 第一PCB的表面积小于第二PCB的表面积。 第二个PCB用作电子元件布局的主要电路板。 优选地，复合或高压电路设置在第一PCB上，并且其它电路设置在第二PCB上。

公开(公告)号：US07106408B2

公开(公告)日：2006-09-12

申请号：US10806097

申请日：2004-03-23

Applicant: Kazuhiro Ogawa ,  Kazuhiko Yanagawa

Inventor： Kazuhiro Ogawa ,  Kazuhiko Yanagawa

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  G02F1/134363 ,  H01L2924/0002 ,  H05K1/117 ,  H05K3/244 ,  H05K3/28 ,  H05K3/323 ,  H05K3/3452 ,  H05K3/361 ,  H05K2201/09709 ,  H05K2201/10659 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A liquid crystal display device which provides reliable connection between a semiconductor device and a printed circuit board includes a liquid crystal display panel, a printed circuit board disposed close to the liquid crystal display panel, and a semiconductor device of a film carrier type which is disposed to lie between the liquid crystal display panel and the printed circuit board, and terminals of the semiconductor device are respectively connected by an anisotropic conductive film to terminals of the printed circuit board that are disposed in opposition to the respective terminals of the semiconductor device.

Abstract translation: 提供半导体器件和印刷电路板之间的可靠连接的液晶显示装置包括液晶显示面板，靠近液晶显示面板设置的印刷电路板，以及设置在薄膜载体型的半导体器件 位于液晶显示面板和印刷电路板之间，并且半导体器件的端子分别通过各向异性导电膜连接到与半导体器件的各个端子相对设置的印刷电路板的端子。