公开(公告)号：US07812430B2

公开(公告)日：2010-10-12

申请号：US12042125

申请日：2008-03-04

申请人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

发明人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/4951 ,  H01L23/49551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

摘要翻译： 揭示了具有降压挡板的引线架和利用其的半导体封装。 引线框架主要包括形成在第一平面上的多个引线，平行地形成在第二平面上的挡板和形成在第一平面和第二平面之间的内部连接杆。 内部连接杆具有至少两个或更多个绕组，例如“S”形，以将挡板板柔性地连接到相邻的引线之间。 因此，内部连接杆可以减少在挡板形成下降期间所连接的引线的移动和扭转。

公开(公告)号：US07776649B1

公开(公告)日：2010-08-17

申请号：US12434126

申请日：2009-05-01

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/014

摘要： A method for fabricating a plurality of wafer level chip scale packages is revealed. A bumped wafer is laminated with a mold plate with a protection film placed thereon to partially embed the bumps of the wafer into the protection film and to form an underfill gap between the wafer and the protection film. By a first sawing step, the wafer fixed by the protection film is singulated into a plurality of chips having sides between the active surface and the back surface and also a filling gap is formed between the sides. Then, an encapsulant is formed on the protection film where the encapsulant fills the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps. By separating the encapsulant from the protection film and a second sawing step, the mold plate and the protection film are removed, and the encapsulant is singulated into a plurality of individual wafer level chip scale packages.

摘要翻译： 揭示了制造多个晶片级芯片级封装的方法。 凸起的晶片与其上放置有保护膜的模板层压，以将晶片的凸块部分地嵌入保护膜中并在晶片和保护膜之间形成底部填充间隙。 通过第一锯切步骤，由保护膜固定的晶片被分割成具有在活性表面和背面之间的侧面的多个芯片，并且在两侧之间形成填充间隙。 然后，在保护膜上形成密封剂，其中密封剂通过填充间隙填充底部填充间隙，以完全封装凸块的芯片和非嵌入部分。 通过将密封剂与保护膜分开并进行第二锯切步骤，去除模板和保护膜，并将密封剂分成多个单独的晶片级芯片级封装。

公开(公告)号：US07692313B2

公开(公告)日：2010-04-06

申请号：US12042105

申请日：2008-03-04

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/13 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2203/1572 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

摘要： A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a die-attaching layer are formed on the other surface of the core. The first solder mask has a thickness difference with respect to the second solder mask in a manner to reduce the warpage of the substrate caused by thermal stresses due to temperature differences can be well under control. Therefore, the manufacturing cost of the substrate can be lower without adding extra stiffeners to achieve substrate warpage control during semiconductor packaging processes.

摘要翻译： 揭示了具有降低的基板翘曲的基板和利用该基板的半导体封装。 基板主要包括在芯的一个表面上形成布线层和第一焊料掩模的芯，并且在芯的另一个表面上形成第二焊料掩模和管芯附着层。 第一焊料掩模具有相对于第二焊料掩模的厚度差，以减少由于温度差导致的热应力引起的基板的翘曲的方式可以很好地控制。 因此，在半导体封装工序中，不添加额外的加强件来实现基板翘曲控制，基板的制造成本可以较低。

公开(公告)号：US07663204B2

公开(公告)日：2010-02-16

申请号：US11790826

申请日：2007-04-27

申请人： Hung-Hsin Hsu ,  Chih-Wei Wu

发明人： Hung-Hsin Hsu ,  Chih-Wei Wu

IPC分类号： H01L29/00 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/3121 ,  H01L23/5382 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes.

摘要翻译： 公开了一种用于多芯片堆叠的基板和利用该基板及其应用的多芯片堆叠封装。 基板包括第一引线接合指状物，第二引线键合指状物，构造成用于电传输的迹线和在同一表面上的环形布线。 第一引线接合指和第二引线接合指彼此相邻并且与基板的管芯附接区相邻。 环路布线将第一引线接合指状物与第二引线键合指针串联连接并连接至迹线。 当至少两个芯片堆叠在芯片安装区域上并且分别电连接到第一和第二引线键合手指时，环路布线可以选择性地断开。 因此，如果其中一个芯片发生故障，则芯片可以分别且独立地操作而没有相互干扰。 此外，由于可以在模制之后修复并且在半导体封装工艺期间不去除任何接合线，所以应用使用基板的多芯片堆叠封装是有价值的。

公开(公告)号：US07633160B1

公开(公告)日：2009-12-15

申请号：US12269440

申请日：2008-11-12

申请人： Chuang-Fa Lee ,  Chao-Hsiang Leu ,  Tseng-Shin Chiu

发明人： Chuang-Fa Lee ,  Chao-Hsiang Leu ,  Tseng-Shin Chiu

IPC分类号： H01L23/498

CPC分类号： H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A window-type semiconductor package is disclosed to avoid peeling at the moldflow entrance, primarily comprising a substrate, a chip with the active surface attached to the substrate, a die-attaching layer bonding the active surface of the chip to a substrate core of the substrate, a plurality of bonding wires, and an encapsulant. The substrate core has a slot. One end of the slot outside the chip is formed as a moldflow entrance with two or more moldflow blocking lumps protrusively disposed on the substrate core and located at the intersections between one edge of the chip and the two opposing sides of the slot adjacent to the moldflow entrance. Accordingly, the moldflow pressures exerting at the die-attaching layer are blocked to avoid the peeling of the die-attaching layer at the moldflow entrance and to keep a constant die-attaching gap.

摘要翻译： 公开了一种窗型半导体封装，以避免在模流入口处的剥离，主要包括基板，具有附着到基板的活性表面的芯片，将芯片的有源表面粘合到芯片的基板芯的芯片附着层 基板，多根接合线和密封剂。 衬底芯具有槽。 芯片外部的槽的一端形成为具有两个或更多个模流阻塞块的模流入口，该两个或更多个模流阻塞块突出地设置在衬底芯上，并且位于芯片的一个边缘和与模流相邻的槽的两个相对侧 入口。 因此，在模具附着层施加的模具流动压力被阻挡，以避免模具附着层在模具流入口处的剥离，并且保持恒定的模具附着间隙。

公开(公告)号：US20090298233A1

公开(公告)日：2009-12-03

申请号：US12240499

申请日：2008-09-29

申请人： Chin-Ti Chen

发明人： Chin-Ti Chen

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L2224/73203

摘要： The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements.

摘要翻译： 本发明公开了一种制造半导体元件的方法，包括以下步骤：在其上表面上提供具有布线图案的基板，将晶片与基板电连接以进行信号输入和输出; 将树脂填充到晶片和轮胎基板之间以将晶片固定到基板; 以及将晶片和衬底的组合分离成多个半导体元件。 因此，本发明可以简化制造工艺或半导体元件。

公开(公告)号：US20090294933A1

公开(公告)日：2009-12-03

申请号：US12240362

申请日：2008-09-29

申请人： Chin-Ti Chen

发明人： Chin-Ti Chen

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49575 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted.

摘要翻译： 本发明公开了一种引线框架和芯片封装结构，其包括多个引线，其包括多个内引线和多个外引线; 布置在所述内引线的一部分上的多个芯片; 多个连接线将芯片电连接到其它内部引线; 支撑构件，其布置在所述内引线的下表面上并且具有带开口的填充物，其中所述开口的所述背面面向所述内引线; 以及覆盖引线，芯片，连接线和支撑构件的树脂密封剂，并且用外部引线的一部分填充填充物，并且露出支撑构件的表面的一部分。 此外，本发明还公开了一种用于制造引线框架和芯片封装结构的方法，从而促进了芯片封装的质量。

公开(公告)号：US07622794B1

公开(公告)日：2009-11-24

申请号：US12133892

申请日：2008-06-05

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, the thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.

摘要翻译： 揭示了芯片引线（COL）多芯片封装，主要包括多个引线，设置在第一引线上的第一芯片，堆叠在第一芯片上的一个或多个第二芯片和密封剂。 引线具有封装在密封剂内部的多个内部引线，其中内部引线完全形成在朝向并平行于密封剂的底表面的凹陷平面上。 位于密封剂顶表面的内部引线之间的高度是内部引线和底部表面之间的高度的三倍或更大。 由于第二芯片的数量和厚度受到控制，所以密封剂的顶表面与最邻近的第二芯片之间的厚度与密封剂的内部引线和底部表面之间的厚度大致相同 。 因此，密封剂中引线没有下弯曲的内部引线可平衡上下模流，并承载更多的芯片而不会移位或倾斜。

公开(公告)号：US20090283878A1

公开(公告)日：2009-11-19

申请号：US12122946

申请日：2008-05-19

申请人： Wen-Jeng FAN ,  Yu-Mei HSU

发明人： Wen-Jeng FAN ,  Yu-Mei HSU

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.

摘要翻译： 显示了具有封装引线框的LOC半导体封装。 LOC半导体封装主要包括多个引线框的引线，至少一个连接条，芯片和封装上述部件的密封剂。 每个引线都有一个粘结手指。 连接杆具有虚拟手指，其中虚拟手指线性地设置在接合指的配置区域的一侧。 该芯片具有带有接合指状物的活性表面。 当虚设手指和结合指状物通过管芯附着层设置在有效表面上方时，虚拟手指与活动表面的一个边缘相邻。 接合指状物与接合焊盘电连接。 虚拟手指将承受集中应力，以避免活动表面上的粘结指状物由于外部应力而分层或断裂，并避免对引线布局的干扰。

公开(公告)号：US07619307B1

公开(公告)日：2009-11-17

申请号：US12133898

申请日：2008-06-05

申请人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

发明人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.

摘要翻译： 揭示了一种基于引线框架的半导体封装和封装的引线框架。 半导体封装主要包括引线框架的包括一个或多个第一引线，一个或多个第二引线和布置在第一引线和第二引线之间的支撑杆的部分，还包括附接到第一引线，第二引线和 支撑杆，多根接合线和密封剂。 支撑杆具有从第一接合指和第二接合指突起的延伸部分，并且连接到密封剂的非引线侧，其中延伸部具有拱形弯曲部以吸收拉应力并阻止应力传递。 在沿着密封剂的非引线侧修整支撑杆时不会产生由支撑杆分层引起的裂纹。 期望地防止沿支撑杆的裂纹到芯片下方的芯片接合平面的水分渗透。