公开(公告)号：US20240012051A1

公开(公告)日：2024-01-11

申请号：US18448265

申请日：2023-08-11

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Tripti Gupta

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/04

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31727 ,  G06F1/04

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

公开(公告)号：US20230421101A1

公开(公告)日：2023-12-28

申请号：US18463212

申请日：2023-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B2200/0082

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US11855527B1

公开(公告)日：2023-12-26

申请号：US17834174

申请日：2022-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Ranajay Mallik ,  Akshat Jain

IPC: H02M1/42 ,  H02M1/12 ,  H02M7/217

CPC classification number: H02M1/4216 ,  H02M1/12 ,  H02M1/4225 ,  H02M1/4233 ,  H02M7/2173 ,  H02M7/2176 ,  H02M1/42 ,  H02M7/217

Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

公开(公告)号：US20230412155A1

公开(公告)日：2023-12-21

申请号：US18323998

申请日：2023-05-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin JAIN ,  Anand KUMAR ,  Kallol CHATTERJEE

IPC: H03K3/03 ,  H03K3/012 ,  H03K3/354

CPC classification number: H03K3/0307 ,  H03K3/3545 ,  H03K3/012

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

公开(公告)号：US20230410862A1

公开(公告)日：2023-12-21

申请号：US18136491

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/16 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/16 ,  G11C8/08 ,  G11C7/12

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：US20230402364A1

公开(公告)日：2023-12-14

申请号：US18451022

申请日：2023-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Luca Maria Carlo DI DIO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49872 ,  H01L23/49861 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49586 ,  H01L23/49582

Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.

公开(公告)号：US11836346B2

公开(公告)日：2023-12-05

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20230387783A1

公开(公告)日：2023-11-30

申请号：US18234137

申请日：2023-08-15

Applicant: STMicroelectronics International N.V.

Inventor： Akshat JAIN

IPC: H02M1/08 ,  H02M1/32 ,  H03K17/082 ,  H05B6/10

CPC classification number: H02M1/08 ,  H02M1/32 ,  H03K17/0828 ,  H05B6/108 ,  H02M7/04

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

公开(公告)号：US20230375617A1

公开(公告)日：2023-11-23

申请号：US18362550

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Shalini Pathak

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/318536 ,  G01R31/318555 ,  G01R31/318533 ,  G01R31/317 ,  G01R31/318558 ,  G01R31/31853 ,  G01R31/318335 ,  G01R31/318566

Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

公开(公告)号：US11823771B2

公开(公告)日：2023-11-21

申请号：US17158875

申请日：2021-01-26

Applicant: STMicroelectronics International N.V. ,  STMICROELECTRONICS S.r.l.

Inventor： Nitin Chawla ,  Thomas Boesch ,  Anuj Grover ,  Surinder Pal Singh ,  Giuseppe Desoli

IPC: G11C8/04 ,  G06N3/02

CPC classification number: G11C8/04 ,  G06N3/02

Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.