公开(公告)号：US20240136417A1

公开(公告)日：2024-04-25

申请号：US18395616

申请日：2023-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

公开(公告)号：US11968911B2

公开(公告)日：2024-04-23

申请号：US17518571

申请日：2021-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.

公开(公告)号：US20240128214A1

公开(公告)日：2024-04-18

申请号：US18398204

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L2224/0391 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.

公开(公告)号：US11961889B2

公开(公告)日：2024-04-16

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/41 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US11956974B2

公开(公告)日：2024-04-09

申请号：US17074584

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh

IPC: H01L29/06 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/30 ,  H10B61/22 ,  H10B63/80 ,  H10N50/01 ,  H10N70/011

Abstract: The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.

公开(公告)号：US11956973B2

公开(公告)日：2024-04-09

申请号：US17369917

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.

公开(公告)号：US11956972B2

公开(公告)日：2024-04-09

申请号：US17228720

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

公开(公告)号：US20240111220A1

公开(公告)日：2024-04-04

申请号：US17979765

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Yu-Wei Cheng

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: An overlay target that includes a plurality of working zones and a plurality of line segments. The line segments in each of the working zones have a plurality of widths and are parallel to each other.

公开(公告)号：US11950513B2

公开(公告)日：2024-04-02

申请号：US17857185

申请日：2022-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/01 ,  H01F10/32 ,  H10N50/80

CPC classification number: H10N50/01 ,  H01F10/3254 ,  H01F10/329 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US11950431B2

公开(公告)日：2024-04-02

申请号：US18073574

申请日：2022-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/14 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/552 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/552 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.