中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

193 records (took 0.023 seconds)

    Cationic conjugated polymers suitable for strand-specific polynucleotide detection in homogeneous and solid state assays
    141.
    发明申请
    Cationic conjugated polymers suitable for strand-specific polynucleotide detection in homogeneous and solid state assays 有权
    阳离子共轭聚合物适用于在均相和固相测定中的链特异性多核苷酸检测

    公开(公告)号：US20060183140A1

    公开(公告)日：2006-08-17

    申请号：US11329495

    申请日：2006-01-10

    Applicant: Guillermo Bazan ,  Bin Liu

    Inventor： Guillermo Bazan ,  Bin Liu

    IPC: C12Q1/68 ,  C08G63/91

    CPC classification number: C08G61/02 ,  C08G61/122 ,  C08G61/123 ,  C12Q1/6818 ,  C12Q1/6837 ,  G01N21/6428 ,  G01N21/6452 ,  G01N2021/6419 ,  G01N2021/6439 ,  C12Q2563/131 ,  C12Q2537/119 ,  C12Q2525/107

    Abstract: The invention further relates to polycationic multichromophores, which may be conjugated polymers, and methods, articles and compositions employing them as described herein. In some aspects, the invention relates to methods, articles and compositions for the detection and analysis of biomolecules in a sample. Provided assays include those determining the presence of a target biomolecule in a sample or its relative amount, or the assays may be quantitative or semi-quantitative. The methods can be performed on a substrate. The methods can be performed in an array format on a substrate, which can be a sensor. In some embodiments, detection assays are provided employing sensor biomolecules that do not comprise a fluorophore that can exchange energy with the cationic multichromophore. In some aspects biological assays are provided in which energy is transferred between one or more of the multichromophore, a label on the target biomolecule, a label on the sensor biomolecule, and/or a fluorescent dye specific for a polynucleotide, in all permutations. The multichromophore may interact at least in part electrostatically with the sensor and/or the target, and an increase in energy transfer with the polymer may occur upon binding of the sensor and the target. Other variations of the inventions are described further herein.

    Abstract translation: 本发明还涉及可以是共轭聚合物的阳离子多色素，以及如本文所述使用它们的方法，制品和组合物。 在一些方面，本发明涉及用于检测和分析样品中生物分子的方法，制品和组合物。 提供的测定包括确定样品中靶生物分子的存在或其相对量的那些，或者测定可以是定量或半定量的。 该方法可以在衬底上进行。 这些方法可以以阵列格式在基底上进行，其可以是传感器。 在一些实施方案中，使用不包含能够与阳离子多重色素交换能量的荧光团的传感器生物分子来提供检测测定。 在一些方面，提供生物测定，其中在所有置换中，能量在一个或多个多色素，目标生物分子上的标记，传感器生物分子上的标记和/或多核苷酸特异的荧光染料之间转移。 多重色淀可以至少部分地与传感器和/或靶相互作用，并且当传感器和目标物结合时，聚合物的能量传递的增加可能发生。 本文进一步描述了本发明的其它变型。

    Interprocessor communication protocol providing intelligent targeting of nodes
    144.
    发明申请
    Interprocessor communication protocol providing intelligent targeting of nodes 失效
    处理器间通信协议提供节点的智能目标

    公开(公告)号：US20050076122A1

    公开(公告)日：2005-04-07

    申请号：US10678976

    申请日：2003-10-03

    Applicant: Charbel Khawand ,  Jianping Miller ,  Jean Khawand ,  Bin Liu

    Inventor： Charbel Khawand ,  Jianping Miller ,  Jean Khawand ,  Bin Liu

    IPC: H04L29/08 ,  G06F15/173

    CPC classification number: H04L67/14 ,  H04L69/329

    Abstract: An IPC protocol/network allows for intelligent targeting of nodes in order to reduce overhead and provide for improved power management. The IPC server keeps track of the IPC network's node activity and using an operational state table (2000) it can determine which node can handle a service request (e.g., MP3 decode). By keeping track of the current operational condition of the nodes within the network, the processors can have better battery life and application latency can be improved. The IPC server will keep track not only of which nodes can handle which services, but it will also know which node can handle the service request given its knowledge of the operational state of each of the nodes.

    Abstract translation: IPC协议/网络允许节点的智能目标，以减少开销并提供改进的电源管理。 IPC服务器跟踪IPC网络的节点活动并使用操作状态表（2000），它可以确定哪个节点可以处理服务请求（例如，MP3解码）。 通过跟踪网络中节点的当前操作条件，处理器可以具有更好的电池寿命并且可以提高应用延迟。 IPC服务器不仅将跟踪哪些节点可以处理哪些服务，而且还将知道哪个节点可以处理服务请求，因为它知道每个节点的操作状态。

    Receiver architecture employing low intermediate frequency and complex filtering
    145.
    发明授权
    Receiver architecture employing low intermediate frequency and complex filtering 失效
    接收机架构采用低中频和复杂滤波

    公开(公告)号：US06778594B1

    公开(公告)日：2004-08-17

    申请号：US09592016

    申请日：2000-06-12

    Applicant: Bin Liu

    Inventor： Bin Liu

    IPC: H04B138

    CPC classification number: H04L27/22 ,  H03D3/009

    Abstract: A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator. Although a low IF is not generally understood to promote the image rejection performance of a receiver, substantial image rejection is afforded by the polyphase filter, thereby enabling the receiver to be realized almost entirely as a monolithic integrated semiconductor device.

    Abstract translation: 一种以相对低的中频（IF）和多相滤波器为特征的通信接收机架构。 接收机包括耦合到载波信号的输入放大器。 相应的I和Q解调器耦合到输入放大器的输出端。 正交本地振荡器（LO）发生器向I解调器提供相应的LO_I和LO_Q输入，并向I解调器和Q解调器提供LO_Q输入。 正交LO发生器由锁相LO驱动，LO频率使得在一个实施例中，IF的IF约为1MHz。 I解调器和Q解调器输出通过相应的A / D转换器应用于多相滤波器。 多相滤波器输出由数字I / Q解调器处理。 虽然通常不理解低IF以促进接收机的镜像抑制性能，但是由多相滤波器提供了大量的图像抑制，从而使接收机几乎完全可以实现为单片集成半导体器件。

    Image-rejection I/Q demodulators
    146.
    发明授权
    Image-rejection I/Q demodulators 有权
    图像抑制I / Q解调器

    公开(公告)号：US06560449B1

    公开(公告)日：2003-05-06

    申请号：US09591925

    申请日：2000-06-12

    Applicant: Bin Liu

    Inventor： Bin Liu

    IPC: H04B110

    CPC classification number: H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0024

    Abstract: In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.

    Abstract translation: 在用于正交解调的通信接收机中，用于减小接收机的图像响应的反馈技术。 通信接收机包括I解调器和Q解调器。 本地振荡器（LO）信号由PLL提供给正交LO发生器，其向I解调器提供LO_I信号，并向Q解调器提供LO_Q信号。 LO_I和LO_Q信号是LO信号的幅度和相位控制版本。 图像/信号比（I / S）检测器检测I解调器和Q解调器的各个输出端之间的相对相位差和相对幅度差，并将幅度控制信号和相位控制信号施加到对应的幅度控制， 正交LO发生器的相位控制输入。 I / S检测器在接收数据包之间的间隔间隔期间校准正交LO发生器。 来自I / S检测器的控制信号以减少通信接收机的图像响应的方式调节LO_I和LO_Q信号的相对幅度和相位。

    High noise rejection voltage-controlled ring oscillator architecture
    147.
    发明授权
    High noise rejection voltage-controlled ring oscillator architecture 有权

    公开(公告)号：US06414557B1

    公开(公告)日：2002-07-02

    申请号：US09507114

    申请日：2000-02-17

    Applicant: Bin Liu

    Inventor： Bin Liu

    IPC: H03B502

    CPC classification number: H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/7203 ,  H03K3/0231 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0995

    Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources reduce the coupling of noise from the first power supply terminal to the output. The third current source reduces the coupling of noise from the second power supply terminal to the output.

    Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching
    148.
    发明授权
    Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching 失效
    使用单步蚀刻在半导体存储器中制造冠状电容器的方法

    公开(公告)号：US5804489A

    公开(公告)日：1998-09-08

    申请号：US679196

    申请日：1996-07-12

    Applicant: Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

    Inventor： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L27/10817

    Abstract: The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

    Abstract translation: 本发明是在半导体存储器中制造冠状电容器的方法。 使用单步蚀刻来超越DRAM单元中的电容器。 该方法可以使用侧壁聚合物和蚀刻副产物作为掩模形成侧壁聚合物并在第一多晶硅的表面上蚀刻副产物，以形成具有支柱的冠状电容器。 此外，本发明可以在相同的步骤中形成冠状结构和柱，冠状结构和柱增加电容器的表面积。 因此，本发明将增加电容器的性能。

    Method for fabricating a semiconductor memory cell in a DRAM
    149.
    发明授权
    Method for fabricating a semiconductor memory cell in a DRAM 失效
    在DRAM中制造半导体存储单元的方法

    公开(公告)号：US5780339A

    公开(公告)日：1998-07-14

    申请号：US850908

    申请日：1997-05-02

    Applicant: Bin Liu ,  Wen-Jya Liang ,  Yeh-Sen Lin

    Inventor： Bin Liu ,  Wen-Jya Liang ,  Yeh-Sen Lin

    IPC: H01L21/8242

    CPC classification number: H01L27/10852

    Abstract: This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.

    Abstract translation: 本发明是一种在DRAM中制造半导体存储单元的方法。 本发明利用插塞技术和氮化物侧壁间隔物来改善深层接触蚀刻损伤并减少典型的着陆焊盘工艺的掩模步骤的数量。 因此，本发明的方法允许制造半导体存储单元，其减少由于存储节点的接触孔的高纵横比引起的困难。

Patent Agency Ranking