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公开(公告)号：US6004875A
公开(公告)日：1999-12-21
申请号：US558777
申请日：1995-11-15
IPC分类号： H01L21/311 , H01L21/318
CPC分类号： H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
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142.发明授权
公开(公告)号：US5909202A
公开(公告)日：1999-06-01
申请号：US24938
申请日：1998-02-17
申请人： David A. Cathey
发明人： David A. Cathey
CPC分类号： H01J29/94 , H01J2329/00
摘要： A wire serves as a gettering material which is wire-bonded to electrical connections which lead outside of a vacuum sealed package. The wire can be activated to create and maintain a high integrity vacuum environment. The "getter" can be either heat activated or evaporated by the passing of an AC or DC current through the wire.
摘要翻译： 线用作吸气材料，其被引线接合到引导到真空密封包装之外的电连接。 电线可以被激活以产生和保持高完整性的真空环境。 “吸气剂”可以通过交流或直流电流通过电线而被激活或蒸发。
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公开(公告)号：US5885477A
公开(公告)日：1999-03-23
申请号：US782531
申请日：1997-01-10
IPC分类号： H01L21/311 , H01L21/3213 , C09K13/04 , C09K13/06 , C09K13/08
CPC分类号： H01L21/31111 , H01L21/02071 , Y10S148/051 , Y10T428/24802
摘要： The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.
摘要翻译： 本发明涉及一种用于半导体材料的新型蚀刻工艺，其抑制金属腐蚀，包括预处理材料，优选用表面活性剂，然后将材料暴露于包含盐，缓冲氧化物蚀刻和任选的表面活性剂 。
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公开(公告)号：US5847515A
公开(公告)日：1998-12-08
申请号：US742771
申请日：1996-11-01
申请人： John K. Lee , David A. Cathey
发明人： John K. Lee , David A. Cathey
CPC分类号： G09G3/2011 , G09G3/22 , H01J31/127 , G09G2300/08 , G09G2320/0606 , G09G2320/0626
摘要： A field emission display includes a display screen and a cathodoluminescent coating disposed on a conductive inner surface of the display screen. An extraction grid is disposed a predetermined distance away from the inner surface and has a plurality of openings. A plurality of emitters are each aligned with a corresponding one of the openings and are arranged in sets that include at least one emitter. A plurality of emitter driver circuits are each coupled to the emitters in a corresponding one of the sets. Each of the driver circuits receives a control signal having first and second values. The drive circuits drive the emitters such that the display screen displays an image having a first brightness level when the control signal has the first value, and drives the emitters such that the display screen displays an image having a second brightness level when the control signal has the second value. The ratio of the second brightness level to the first brightness level is significantly greater than the ratio of the second value of the control signal to the first value. In one aspect of the invention, each of the driver circuits includes an impedance element that has a nonlinear current-voltage characteristic to give the described ratios.
摘要翻译： 场发射显示器包括显示屏和设置在显示屏的导电内表面上的阴极发光涂层。 提取格栅布置成离开内表面预定距离并且具有多个开口。 多个发射器各自与对应的一个开口对准，并且被设置成包括至少一个发射器的组。 多个发射极驱动电路各自耦合到相应的一组中的发射器。 每个驱动电路接收具有第一和第二值的控制信号。 驱动电路驱动发射器，使得当控制信号具有第一值时，显示屏幕显示具有第一亮度级别的图像，并且驱动发射器，使得当控制信号具有第二亮度级别时，显示屏幕显示具有第二亮度级别的图像 第二个值。 第二亮度水平与第一亮度水平的比率显着大于控制信号的第二值与第一值的比值。 在本发明的一个方面中，每个驱动电路包括一个阻抗元件，该阻抗元件具有非线性电流 - 电压特性以给出所述的比率。
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145.发明授权Fiber spacers in large area vacuum displays and method for manufacture of same 失效大面积真空显示器中的纤维间隔物及其制造方法
公开(公告)号：US5795206A
公开(公告)日：1998-08-18
申请号：US528761
申请日：1995-09-15
申请人： David A. Cathey , Charles M. Watkins , Darryl M. Stansbury , James J. Hofmann , Robert T. Rasmussen , Surjit S. Chadha
发明人： David A. Cathey , Charles M. Watkins , Darryl M. Stansbury , James J. Hofmann , Robert T. Rasmussen , Surjit S. Chadha
CPC分类号： H01J9/242 , H01J29/028 , H01J29/864 , H01J31/123 , H01J31/127 , H01J9/185 , H01J2329/8625 , H01J2329/863 , H01J2329/8635 , H01J2329/864 , H01J2329/8645 , H01J2329/866 , Y10T29/4981
摘要： A process is provided for forming spacers useful in large area displays. The process comprises steps of: forming bundles or boules comprising fiber strands which are held together with a binder; slicing the bundles or boules into slices; adhering the slices on an electrode plate of the display; and removing the binder. In the step of forming bundles or boules comprising fiber strands, the function of the binder is initially or fully performed by glass tubings surrounding the glass fibers. The clad glass of the envelopes etches more readily than the core glass.
摘要翻译： 提供用于形成用于大面积显示器的间隔物的方法。 该方法包括以下步骤：形成包含与粘合剂保持在一起的纤维束的束或毛粒; 将束或碎片切成片; 将切片粘附在显示器的电极板上; 并移除粘合剂。 在形成包含纤维束的束或毛坯的步骤中，粘合剂的功能由围绕玻璃纤维的玻璃管开始或完全进行。 信封的复合玻璃比核心玻璃更容易蚀刻。
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公开(公告)号：US5751262A
公开(公告)日：1998-05-12
申请号：US921772
申请日：1997-08-15
CPC分类号： G01R31/257 , G01R35/002 , Y10S345/904
摘要： A method of electrically testing pixel functionality is provided comprising releasably disposing a wafer in a socket. The wafer has at least one baseplate comprised of cathode emitters arranged in pixels. The socket has pads. The socket pads are contacted with test pins, and each of the pixels is addressed individually, thereby causing the cathode emitters to emit electrons in a current. The current is collected from each of the pixels on an anode screen. Alternatively, the anode card may have pins, and these pins contact pads on the baseplate. The baseplate, or substrate with baseplates, does not require a socket with pins.
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147.发明授权
公开(公告)号：US5741404A
公开(公告)日：1998-04-21
申请号：US653512
申请日：1996-05-24
申请人： David A. Cathey
发明人： David A. Cathey
CPC分类号： H01J37/3423 , C23C14/046 , C23C14/3407 , C23C14/46 , H01J37/34 , H01J2237/3146 , H01J2237/3327
摘要： Disclosed is a multi-plans sputtering target and a method of using the multi-planar sputtering target in PVD sputtering for filling high aspect ratio interconnect structure openings. The multi-planar sputtering target comprises at least two planar sheets of conductive filler material joined together at a common edge with a selected angle between them. The multi-planar sputtering target is situated in a manner whereby an interior portion is facing an semiconductor wafer that is to be filled. The angle of the planes of the multiplanar sputtering target relative to the semiconductor wafer is selected such that a primary concentration of sputtered material is directed in either a normal angle of trajectory, or in a selected angle of trajectory that is selected for filling bottom corners of the interconnect structure opening. An ion acceleration grid can be used to vary the focus of an ion beam on different planar sheets of the multi-planar sputtering target so that different angles of trajectory of sputtered material can be employed in filling the interconnect structure opening. A magnetic field can also be used to correct the occurrence of center to edge non-uniformity.
摘要翻译： 公开了一种多平面溅射靶和在PVD溅射中使用多平面溅射靶用于填充高纵横比互连结构开口的方法。 多平面溅射靶包括至少两个导电填料材料的平面片，其在共同边缘处以它们之间的选定角度连接在一起。 多平面溅射靶以这样的方式设置，即内部部分面向待填充的半导体晶片。 选择多平面溅射靶相对于半导体晶片的平面的角度，使得溅射材料的主要浓度指向正常的轨迹角度，或者选择用于填充底部角落的选定的轨迹角度 互连结构开口。 可以使用离子加速栅格来改变多平面溅射靶的不同平面片上的离子束的焦点，使得可以在填充互连结构开口时采用溅射材料的不同轨迹的角度。 也可以使用磁场来校正中心到边缘不均匀的发生。
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公开(公告)号：US5653619A
公开(公告)日：1997-08-05
申请号：US300985
申请日：1994-09-06
CPC分类号： H01J9/025 , H01J2209/0226 , H01J2329/00
摘要： A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.
摘要翻译： 采用选择性蚀刻和化学机械平面化方法来形成围绕用于场发射显示器的电子发射尖端的自对准栅极和聚焦环结构。 该方法用于构建发射栅极，由此栅极结构能够在阴极尖端产生足以产生电子发射的场强。 门设置在尖端上方的位置，使得栅极物理地截取梁的最外侧部分，但不会引起梁的显着的静电向外发散，从而减小梁的横截面。
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149.发明授权
公开(公告)号：US5438240A
公开(公告)日：1995-08-01
申请号：US232792
申请日：1994-04-22
CPC分类号： H01J1/3042 , H01J9/025 , H01J2201/30407
摘要： A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.
摘要翻译： 一种用于平板显示器的底板，包括相对厚的半导体衬底，其中半导体衬底是通过离子注入而非晶化或通过重结晶重新形成的宏晶多晶衬底，以掩盖晶界，此后可制造冗余电路， 进一步提高产品产量。
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公开(公告)号：US5409563A
公开(公告)日：1995-04-25
申请号：US23935
申请日：1993-02-26
申请人： David A. Cathey
发明人： David A. Cathey
IPC分类号： H01L21/3065 , H01L21/00
CPC分类号： H01L21/3065
摘要： A method for forming high aspect ratio features such as trenches in a semiconductor structure includes dry etching a substrate in a glow discharge system at elevated temperature. With the dry etching carried out at an elevated temperature of between about 300.degree. to 1100.degree. C., the diffusion of a reactant gas into the features is increased and the diffusion of byproduct molecules out of the features is increased. This increases the etch rate for forming the features, and allows features with very high aspect ratio to be formed at a high etch rate.
摘要翻译： 用于形成诸如半导体结构中的沟槽的高纵横比特征的方法包括在高温下在辉光放电系统中干蚀刻衬底。 通过在约300℃至1100℃之间的高温下进行干蚀刻，反应气体扩散到特征中增加，副产物分子扩散到特征之外。 这增加了用于形成特征的蚀刻速率，并且允许以高蚀刻速率形成具有非常高的纵横比的特征。
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