公开(公告)号：US20240113019A1

公开(公告)日：2024-04-04

申请号：US17956775

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohit K. HARAN ,  Nikhil MEHTA ,  Charles H. WALLACE ,  Tahir GHANI ,  Sukru YEMENICIOGLU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L23/5226

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.

公开(公告)号：US20240105597A1

公开(公告)日：2024-03-28

申请号：US17950926

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Robert JOACHIM ,  Shengsi LIU ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/53238

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. An inter-layer dielectric (ILD) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. The dielectric plug portion of the ILD structure is continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines. The dielectric plug portion of the ILD structure has an inwardly tapering profile from top to bottom.

公开(公告)号：US20240055497A1

公开(公告)日：2024-02-15

申请号：US18383370

申请日：2023-10-24

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20240008253A1

公开(公告)日：2024-01-04

申请号：US17855545

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10826

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

公开(公告)号：US20240006531A1

公开(公告)日：2024-01-04

申请号：US17855573

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Cory WEBER ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L29/78 ,  H01L27/13 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/13 ,  H01L27/124 ,  H01L29/66666

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

公开(公告)号：US20240006317A1

公开(公告)日：2024-01-04

申请号：US17855586

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Cory WEBER ,  Rishabh MEHANDRU ,  Wilfred GOMES ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L29/785 ,  H01L21/76898 ,  H01L27/0924 ,  H01L21/823871

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

公开(公告)号：US20240006305A1

公开(公告)日：2024-01-04

申请号：US17855017

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Anand S. MURTHY ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

公开(公告)号：US20230360972A1

公开(公告)日：2023-11-09

申请号：US18221754

申请日：2023-07-13

Applicant: Intel Corporation

Inventor： Oleg GOLONZKA ,  Swaminathan SIVAKUMAR ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L21/76897 ,  H01L21/30625 ,  H01L27/088 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/66545 ,  H01L21/28008 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20230317808A1

公开(公告)日：2023-10-05

申请号：US17700002

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Clifford ONG ,  Sukru YEMENICIOGLU ,  Tahir GHANI ,  Brian GREENE

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

公开(公告)号：US20230317731A1

公开(公告)日：2023-10-05

申请号：US17709378

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/76283

Abstract: Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.