公开(公告)号：US20210126015A1

公开(公告)日：2021-04-29

申请号：US17141495

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: H01L27/11597 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

公开(公告)号：US10910403B2

公开(公告)日：2021-02-02

申请号：US16391479

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: H01L21/02 ,  H01L27/11597 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

公开(公告)号：US10475500B2

公开(公告)日：2019-11-12

申请号：US16111021

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

公开(公告)号：US10446214B1

公开(公告)日：2019-10-15

申请号：US16102053

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

公开(公告)号：US10403336B2

公开(公告)日：2019-09-03

申请号：US15857091

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20190206455A1

公开(公告)日：2019-07-04

申请号：US15857091

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

CPC classification number: G11C7/12 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2293

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20190189211A1

公开(公告)日：2019-06-20

申请号：US15846373

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C14/00 ,  G11C11/22

CPC classification number: G11C14/0027 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2293

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US20190180817A1

公开(公告)日：2019-06-13

申请号：US16279585

申请日：2019-02-19

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

公开(公告)号：US20190067206A1

公开(公告)日：2019-02-28

申请号：US15691055

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Daniele Vimercati

IPC: H01L23/552 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/409

CPC classification number: H01L23/552 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1096 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/82 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10885 ,  H01L27/11507 ,  H01L27/11514

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

公开(公告)号：US20180366189A1

公开(公告)日：2018-12-20

申请号：US16108828

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00 ,  G06F11/10 ,  G11C16/34

CPC classification number: G11C13/0033 ,  G06F11/1068 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/009 ,  G11C16/3418 ,  G11C29/52

Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.