公开(公告)号：US11721399B2

公开(公告)日：2023-08-08

申请号：US17504467

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.

公开(公告)号：US20230245708A1

公开(公告)日：2023-08-03

申请号：US18133103

申请日：2023-04-11

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12015 ,  G11C2207/2254

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.

公开(公告)号：US11714710B2

公开(公告)日：2023-08-01

申请号：US17544772

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Larry J. Koudele ,  Michael Sheperek ,  Patrick R. Khayat ,  Sampath K. Ratnam

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.

公开(公告)号：US11709775B2

公开(公告)日：2023-07-25

申请号：US17694434

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G06F12/0804 ,  G06F3/06 ,  G11C16/30 ,  G11C16/32 ,  G01R19/165 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F12/0804 ,  G01R19/16538 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G06F2212/1032 ,  G11C16/0483

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

公开(公告)号：US11705208B2

公开(公告)日：2023-07-18

申请号：US17530368

申请日：2021-11-18

Applicant: Micron Technology, Inc.

Inventor： Larry J. Koudele ,  Bruce A. Liikanen ,  Michael Sheperek

IPC: G11C16/26 ,  G06F12/02 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F12/0223 ,  G11C16/10 ,  G06F2212/1008 ,  G11C16/0483

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.

公开(公告)号：US11705192B2

公开(公告)日：2023-07-18

申请号：US17124144

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Shane Nowell

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: A block family associated with a memory device is created. The block family is associated with a threshold voltage offset bin. A set of read level voltage offsets is determined such that, applying the set of read level voltage offsets to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate. The determined set of read level offsets is associated with the threshold voltage offset bin by updating a block family metadata.

公开(公告)号：US20230205442A1

公开(公告)日：2023-06-29

申请号：US18118082

申请日：2023-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shane Nowell ,  Michael Sheperek ,  Larry J. Koudele ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0629 ,  G06F3/0679 ,  G06F3/0653 ,  G06F3/0619 ,  G06F3/0659

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

公开(公告)号：US11609706B2

公开(公告)日：2023-03-21

申请号：US16507915

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Larry Koudele

IPC: G06F3/06

Abstract: The present disclosure is directed to placement of samples of a read sample offset operation in a memory sub-system. A processing device determines a shape of a valley to be subject to a read sample offset operation, where the valley corresponds to at least one programming distribution of a memory sub-system. The processing device selects a sampling rule from a set of sampling rules based on the shape of the valley. The processing device executes the read sample offset operation in accordance with the sampling rule.

公开(公告)号：US11600333B2

公开(公告)日：2023-03-07

申请号：US17395067

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/14 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04

Abstract: A first logical page type and a second logical page type each comprising a plurality of programming distributions of a memory device are identified. A determination is made that the bit error rate (BER) for the first logical page type is less than a BER for the second logical page type. A set of rules corresponding to a determination that the BER for the first logical page type is less than the BER for the second logical page type is identified. A program targeting rule of the set of rules is determined based on a valley between an erase distribution and a programming distribution adjacent to the erase distribution having a lowest valley margin of a plurality of valley margins corresponding to the plurality of programming distributions of the memory device. Based on the program targeting rule, a program targeting operation is performed to adjust a voltage associated with one or more programming distributions of the memory device.

公开(公告)号：US11573720B2

公开(公告)日：2023-02-07

申请号：US16947819

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steven Michael Kientz ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G01K3/04 ,  G06F1/324 ,  G06F1/3228

Abstract: A includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to: initialize a block family associated with the memory device; initialize a timer at initialization of the block family; and aggregate temperature values received from sensor(s) of the memory device over time to generate an aggregate temperature. Responsive to programming a page residing on the memory device, the processing device associates the page with the block family. The processing device closes the block family in response to the aggregate temperature being greater than a first temperature value and the timer reaching a first time value. The processing device closes the block family in response to the aggregate temperature being less than or equal to the first temperature value and the timer reaching a second time value that is greater than the first time value.