公开(公告)号：US12176061B2

公开(公告)日：2024-12-24

申请号：US18420404

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20240260171A1

公开(公告)日：2024-08-01

申请号：US18632122

申请日：2024-04-10

Applicant: Micron Technology, Inc.

Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

IPC: H05K1/02 ,  H04B3/32 ,  H04B3/487

CPC classification number: H05K1/0233 ,  H04B3/32 ,  H04B3/487 ,  H05K1/0228

Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

公开(公告)号：US12051462B2

公开(公告)日：2024-07-30

申请号：US17889154

申请日：2022-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： M. Ataul Karim ,  Timothy M. Hollis

IPC: G11C11/00 ,  G11C11/4093 ,  G11C11/56 ,  H04L27/08

CPC classification number: G11C11/4093 ,  G11C11/565 ,  H04L27/08

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

公开(公告)号：US11996359B2

公开(公告)日：2024-05-28

申请号：US18312801

申请日：2023-05-05

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US11699477B2

公开(公告)日：2023-07-11

申请号：US17499025

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: G11C11/406 ,  G11C29/42 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C7/109 ,  G11C7/1048 ,  G11C7/1063 ,  G11C11/40622 ,  G11C29/42

Abstract: A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

公开(公告)号：US20230004492A1

公开(公告)日：2023-01-05

申请号：US17863987

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806 ,  H04L5/00

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US20220400038A1

公开(公告)日：2022-12-15

申请号：US17851533

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G06F13/38 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US11527508B2

公开(公告)日：2022-12-13

申请号：US17174177

申请日：2021-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

公开(公告)号：US20220392518A1

公开(公告)日：2022-12-08

申请号：US17889154

申请日：2022-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： M. Ataul Karim ,  Timothy M. Hollis

IPC: G11C11/4093 ,  H04L27/08 ,  G11C11/56

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

公开(公告)号：US20220335000A1

公开(公告)日：2022-10-20

申请号：US17850927

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G06F11/10 ,  G11C7/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.