公开(公告)号：US07291527B2

公开(公告)日：2007-11-06

申请号：US11220451

申请日：2005-09-07

申请人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

发明人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

公开(公告)号：US07226830B2

公开(公告)日：2007-06-05

申请号：US11118237

申请日：2005-04-29

申请人： Luigi Colombo ,  James Joseph Chambers ,  Mark Robert Visokay

发明人： Luigi Colombo ,  James Joseph Chambers ,  Mark Robert Visokay

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L27/11

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成第一氧化物层。 第一氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

公开(公告)号：US07183221B2

公开(公告)日：2007-02-27

申请号：US10703388

申请日：2003-11-06

申请人： Mark R. Visokay ,  Luigi Colombo

发明人： Mark R. Visokay ,  Luigi Colombo

IPC分类号： H01L21/302

CPC分类号： H01L21/823842

摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

公开(公告)号：US07163877B2

公开(公告)日：2007-01-16

申请号：US10920990

申请日：2004-08-18

申请人： Hiroaki Niimi ,  Luigi Colombo ,  Koji Shimomura ,  Takuya Sugawara ,  Tatsuo Matsudo

发明人： Hiroaki Niimi ,  Luigi Colombo ,  Koji Shimomura ,  Takuya Sugawara ,  Tatsuo Matsudo

IPC分类号： H01L21/21 ,  H01L21/42

CPC分类号： H01L21/022 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/02274 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3115 ,  H01L21/3144 ,  H01L21/3165 ,  H01L29/513 ,  H01L29/517

摘要： A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.

摘要翻译： 一种用于通过暴露于等离子体来修改栅极电介质叠层的方法和系统。 该方法包括提供具有形成在衬底上的高k层的栅极电介质堆叠，从含有惰性气体和含氧气体或含氮气体中的一种的工艺气体产生等离子体，其中工艺气体压力 被选择为相对于等离子体中的离子基团的量来控制中性自由基的量，以及通过将该叠层暴露于等离子体来修改栅极电介质堆叠。

公开(公告)号：US07045431B2

公开(公告)日：2006-05-16

申请号：US10738958

申请日：2003-12-17

申请人： Antonio L. P. Rotondaro ,  Douglas E. Mercer ,  Luigi Colombo ,  Mark Robert Visokay ,  Haowen Bu ,  Malcolm John Bevan

发明人： Antonio L. P. Rotondaro ,  Douglas E. Mercer ,  Luigi Colombo ,  Mark Robert Visokay ,  Haowen Bu ,  Malcolm John Bevan

IPC分类号： H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

摘要翻译： 公开了制造具有高k电介质层的半导体器件的方法。 本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染 工具 封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。 结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

公开(公告)号：US20050106797A1

公开(公告)日：2005-05-19

申请号：US11013221

申请日：2004-12-14

申请人： Luigi Colombo

发明人： Luigi Colombo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate structure, and a silicon nitride encapsulation layer is formed to protect the conditioned sidewalls during manufacturing processing. The conditioning and encapsulation avoid oxidation of gate stack layers, particularly metal gate layers, and also facilitate repairing or restoring stoichiometry of metal and other gate layers that may be damaged or altered during gate patterning.

摘要翻译： 提供了晶体管栅极结构，封装结构和制造技术，其中图案化栅极结构的侧壁通过氮化栅极结构的侧壁进行调节，并且形成氮化硅封装层以在制造处理期间保护经调节的侧壁。 调节和封装避免了栅极堆叠层，特别是金属栅极层的氧化，并且还有助于修复或恢复在栅极图案化期间可能被损坏或改变的金属和其它栅极层的化学计量。

公开(公告)号：US20050090433A1

公开(公告)日：2005-04-28

申请号：US10493558

申请日：2003-11-14

申请人： Luigi Colombo ,  Adriano Malabarba ,  Martin Stogniew

发明人： Luigi Colombo ,  Adriano Malabarba ,  Martin Stogniew

IPC分类号： A61K31/70 ,  A61K31/704 ,  A61K38/12 ,  A61K38/14 ,  A61P31/04

CPC分类号： A61K38/14 ,  A61K31/70 ,  A61K31/704 ,  A61K38/00 ,  A61K2300/00

摘要： The invention provides methods and compositions for treatment of bacterial infections. Methods of the invention include administration of a mixture of dalbavancin multimers and monomers for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Compositions comprise a mixture of dalbavancin multimer and monomer and a stabilizer, such as dextrose.

公开(公告)号：US06876021B2

公开(公告)日：2005-04-05

申请号：US10303560

申请日：2002-11-25

申请人： J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

发明人： J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

摘要翻译： 本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。 本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。 通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

公开(公告)号：US06852645B2

公开(公告)日：2005-02-08

申请号：US10367429

申请日：2003-02-13

申请人： Luigi Colombo ,  James J. Chambers ,  Antonio L. P. Rotondaro ,  Mark R. Visokay

发明人： Luigi Colombo ,  James J. Chambers ,  Antonio L. P. Rotondaro ,  Mark R. Visokay

IPC分类号： C23C28/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/78 ,  H01L21/469

CPC分类号： H01L21/28185 ,  C23C28/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31155 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.

摘要翻译： 本发明涉及在制造半导体器件时形成适用于高k栅极电介质的高品质薄界面氧化物层的方法。 使用含有氧和还原剂的环境来生长层。 氧促进层的生长，而还原剂同时抵消该生长。 因此，可以通过调节还原剂的分压来控制层的生长速度，还原剂的分压是气相中还原剂的分数乘以总压力。 控制和减缓层的生长速率有助于在约850摄氏度或更高的温度下将层的生产达到约10埃或更小的厚度。 在高温下生长层有助于更好地粘合和生产更高质量的层，这又产生更好的性能和更可靠的结果产品。

公开(公告)号：US06828161B2

公开(公告)日：2004-12-07

申请号：US10313068

申请日：2002-12-06

申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。