公开(公告)号：US12067239B2

公开(公告)日：2024-08-20

申请号：US17955907

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/076 ,  G06F11/1004 ,  G06F11/1048

Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

公开(公告)号：US20240087663A1

公开(公告)日：2024-03-14

申请号：US17944135

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Danilo Caraccio ,  Thomas T. Tangelder ,  Jacob S. Robertson ,  James G. Steele ,  Joemar Sinipete

IPC: G11C29/36 ,  G11C29/02 ,  G11C29/42

CPC classification number: G11C29/36 ,  G11C29/022 ,  G11C29/42 ,  G11C2029/3602

Abstract: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.

公开(公告)号：US20240028249A1

公开(公告)日：2024-01-25

申请号：US17868286

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

公开(公告)号：US20230393939A1

公开(公告)日：2023-12-07

申请号：US18204821

申请日：2023-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1028

Abstract: Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.

公开(公告)号：US11782854B2

公开(公告)日：2023-10-10

申请号：US17865341

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F12/10 ,  G06F12/121 ,  G11C16/04

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F12/121 ,  G06F2212/657 ,  G11C16/0483

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

公开(公告)号：US11775382B2

公开(公告)日：2023-10-03

申请号：US17541956

申请日：2021-12-03

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/22

CPC classification number: G06F11/1004 ,  G06F11/1016 ,  G06F11/1044

Abstract: Systems, apparatuses, and methods related to modified parity data using a poison data unit. An example method can include receiving, from a controller of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits comprises one or more erroneous or corrupted bits. The method can further include generating, at an encoder of the memory device, parity data associated with the first set of bits. The method can further include generating, at logic of the memory device, modified parity data with the parity data component and the second set of at least one bit. The method can further include writing the first set of bits and the modified parity data in an array of the memory device.

公开(公告)号：US11741027B2

公开(公告)日：2023-08-29

申请号：US17865341

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F12/10 ,  G06F12/121 ,  G11C16/04

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F12/121 ,  G06F2212/657 ,  G11C16/0483

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

公开(公告)号：US11720163B2

公开(公告)日：2023-08-08

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/32 ,  G06F11/30 ,  G06F1/3234 ,  G06F13/16 ,  G11C5/14 ,  G06F1/30 ,  G06F1/3212 ,  G11C16/30 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20

CPC classification number: G06F1/3275 ,  G06F1/305 ,  G06F1/3212 ,  G06F11/3062 ,  G06F13/1668 ,  G11C5/142 ,  G11C5/144 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20230096375A1

公开(公告)日：2023-03-30

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

公开(公告)号：US20230054662A1

公开(公告)日：2023-02-23

申请号：US17981703

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.