公开(公告)号：US11031414B2

公开(公告)日：2021-06-08

申请号：US16434052

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

公开(公告)号：US11018155B2

公开(公告)日：2021-05-25

申请号：US16812938

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L29/792

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US20210098028A1

公开(公告)日：2021-04-01

申请号：US16585346

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Peng Xu

IPC: G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.

公开(公告)号：US20210050361A1

公开(公告)日：2021-02-18

申请号：US16539700

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Rita J. Klein ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material than may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.

公开(公告)号：US10833205B2

公开(公告)日：2020-11-10

申请号：US16417507

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L21/336 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

公开(公告)号：US10790303B2

公开(公告)日：2020-09-29

申请号：US16793560

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L21/28 ,  H01L21/02 ,  H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200251347A1

公开(公告)日：2020-08-06

申请号：US16854283

申请日：2020-04-21

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11556

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US20200211981A1

公开(公告)日：2020-07-02

申请号：US16235665

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20200161325A1

公开(公告)日：2020-05-21

申请号：US16194946

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  David H. Wells ,  John D. Hopkins ,  Kevin Y. Titus

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/08 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

公开(公告)号：US20190043890A1

公开(公告)日：2019-02-07

申请号：US16158039

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.