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    NON-VOLATILE MEMORY WITH TIER-WISE RAMP DOWN AFTER PROGRAM-VERIFY
    141.
    发明公开
    NON-VOLATILE MEMORY WITH TIER-WISE RAMP DOWN AFTER PROGRAM-VERIFY 审中-公开

    公开(公告)号：US20240071529A1

    公开(公告)日：2024-02-29

    申请号：US17898850

    申请日：2022-08-30

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Dengtao Zhao ,  Xiang Yang

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

    Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE
    142.
    发明公开
    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240071509A1

    公开(公告)日：2024-02-29

    申请号：US17897854

    申请日：2022-08-29

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Jiacen Guo ,  Shubhajit Mukherjee

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459

    Abstract: The techniques include a memory device receiving a data write instruction. The memory device programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format with a first and second SLC data states. In response to the data programmed to the memory cells of the memory blocks reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells, the memory device programs at least some of the memory cells from the SLC format to a two bits per memory cell (MLC) format. When programming from the SLC format to the MLC format, the memory device inhibits programming of some of the memory cells in the first and second SLC data states to form a first MLC data state and programs other memory cells of the SLC data states to form second, third, and fourth MLC data states.

    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE
    143.
    发明公开
    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240071508A1

    公开(公告)日：2024-02-29

    申请号：US17896587

    申请日：2022-08-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Jiacen Guo ,  Takayuki Inoue

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/14 ,  G11C16/3459

    Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE
    144.
    发明公开
    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240069803A1

    公开(公告)日：2024-02-29

    申请号：US17898639

    申请日：2022-08-30

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Wei Cao

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0679

    Abstract: The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry is configured to program the memory cells of at least some of the plurality of memory blocks from the SLC format to a TLC format.

    Non-volatile memory with engineered channel gradient
    146.
    发明授权
    Non-volatile memory with engineered channel gradient 有权

    公开(公告)号：US11881271B2

    公开(公告)日：2024-01-23

    申请号：US17828685

    申请日：2022-05-31

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Xiang Yang ,  Xiaochen Zhu

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

    Abstract: To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.

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