公开(公告)号：US11929419B2

公开(公告)日：2024-03-12

申请号：US17129253

申请日：2020-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/762

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76224 ,  H01L29/4966

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

公开(公告)号：US11908920B2

公开(公告)日：2024-02-20

申请号：US17722787

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30621 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

公开(公告)号：US20230361197A1

公开(公告)日：2023-11-09

申请号：US18354995

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

公开(公告)号：US11784185B2

公开(公告)日：2023-10-10

申请号：US17241841

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165

Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

公开(公告)号：US11757019B2

公开(公告)日：2023-09-12

申请号：US17650942

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

公开(公告)号：US20230207670A1

公开(公告)日：2023-06-29

申请号：US18178140

申请日：2023-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Pei-Hsiu Wu ,  Chih Ping Wang ,  Chih-Han Lin ,  Jr-Jung Lin ,  Yun Ting Chou ,  Chen-Yu Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L29/6681 ,  H01L29/7851 ,  H01L29/0649 ,  H01L29/66636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66545 ,  H01L21/28518

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

公开(公告)号：US11637204B2

公开(公告)日：2023-04-25

申请号：US17113057

申请日：2020-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a semiconductive substrate, a semiconductive fin, a stop layer, a fin isolation structure, and a spacer. The semiconductive fin is over the substrate. The stop layer is between the semiconductive substrate and the semiconductive fin. The fin isolation structure is in contact with the semiconductor fin and over the stop layer. A topmost surface of the fin isolation structure is higher than a topmost surface of the semiconductive fin. The spacer at least partially extends along a sidewall of the fin isolation structure.

公开(公告)号：US20230109951A1

公开(公告)日：2023-04-13

申请号：US18065166

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US11605564B2

公开(公告)日：2023-03-14

申请号：US17120942

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US11594634B2

公开(公告)日：2023-02-28

申请号：US16948039

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8232 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/283 ,  H01L29/423

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.