公开(公告)号：US20200043796A1

公开(公告)日：2020-02-06

申请号：US16286558

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L21/308

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US10516061B2

公开(公告)日：2019-12-24

申请号：US15907008

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ling-Yen Yeh ,  Chih-Sheng Chang ,  Wilman Tsai ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

公开(公告)号：US10157988B1

公开(公告)日：2018-12-18

申请号：US15652607

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wai-Yi Lien ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure includes a conductive plug formed over the first gate structure, and the conductive plug is electrically connected to the first gate structure. The FinFET device structure includes a first spacer layer formed on a sidewall surface of the conductive plug and a source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. The FinFET device structure further includes a first insulation layer formed over the S/D contact structure and a second spacer layer formed on a sidewall surface of the first insulation layer. The conductive plug extends from a first position which is above the first spacer layers to a second position which is above the second spacer layer.

公开(公告)号：US10056498B2

公开(公告)日：2018-08-21

申请号：US15401463

申请日：2017-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ling-Yen Yeh ,  Chih-Sheng Chang ,  Wilman Tsai ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02527 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/66969 ,  H01L29/778

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

公开(公告)号：US12302557B2

公开(公告)日：2025-05-13

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US12237418B2

公开(公告)日：2025-02-25

申请号：US18365315

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/51 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US12224325B2

公开(公告)日：2025-02-11

申请号：US18353027

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US12207478B2

公开(公告)日：2025-01-21

申请号：US17238678

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B61/00 ,  H01L21/02 ,  H01L29/24 ,  H10N50/01

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US20240387658A1

公开(公告)日：2024-11-21

申请号：US18783869

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US20240365559A1

公开(公告)日：2024-10-31

申请号：US18766899

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.