公开(公告)号：US5130666A

公开(公告)日：1992-07-14

申请号：US662243

申请日：1991-02-27

Applicant: Germano Nicollini

Inventor： Germano Nicollini

IPC: H03F3/347 ,  H03F1/08 ,  H03F3/30 ,  H03F3/45

CPC classification number: H03F3/45183 ,  H03F1/086 ,  H03F3/3023 ,  H03F3/45659 ,  H03F2200/261

Abstract: The preamplifier includes a first amplifier stage (M1A, M2A) and a second amplifier stage (M1, M2), both of which are of the differential type, have the same dimensions, have their output nodes connected in parallel to one another, and drive a load formed by a current mirror (M3, M4). A third differential amplifier stage with single-ended output (M6, M7, M8, M9, M10, M11) driven by the current mirror supplies the final output voltage of the preamplifier. The input nodes of the first stage act as input for the differential signal to be amplified, and the input nodes of the second stage are driven respectively by a preset reference voltage (V.sub.CM) and by a voltage (V.sub.x) which is proportional to the final output voltage of the preamplifier. A negative voltage-current feedback is thus obtained, due to the fact that a difference in current is generated between the respective output nodes of the first and second stages; the difference is proportional to the difference between the differential signal to be amplified and the difference between the reference voltage and the voltage which is proportional to the final output voltage (V.sub.x -V.sub.CM).

公开(公告)号：US5126911A

公开(公告)日：1992-06-30

申请号：US385721

申请日：1989-07-26

Applicant: Claudio Contiero ,  Bruno Murari

Inventor： Claudio Contiero ,  Bruno Murari

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H02H11/00

CPC classification number: H01L29/7803 ,  H01L27/0218 ,  H01L27/0266 ,  H01L29/7809 ,  H01L29/7817 ,  H02H11/003 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7831 ,  Y10T307/839

Abstract: An integrated circuit self-protected against a reversal of its supply battery polarity comprises a first DMOS power transistor connected with its source electrode side to an electric load to be driven toward ground, and a second, protective DMOS transistor which is connected with its source electrode side to a positive pole of the battery and with its drain electrode side to the drain electrode of the first transistor. The first and second transistors have in common the drain region formed on a single pod in the semiconductor substrate.

公开(公告)号：US5065240A

公开(公告)日：1991-11-12

申请号：US281017

申请日：1988-12-06

Applicant: Maurizio Zuffada ,  Fabrizio Sacchi

Inventor： Maurizio Zuffada ,  Fabrizio Sacchi

IPC: H04N5/46

CPC classification number: H04N5/46

Abstract: A method, and related device, for automatically selecting the demodulation standard of a video signal, useful with an intermediate frequency demodulator, which has an output for the demodulated signal and a so-called standard selecting input pin, consists of detecting the polarity of the demodulated signal at the output of the demodulator and comparing that polarity with the polarity of the input signal to the demodulator. The voltage value on the standard selecting pin is changed over on detecting a different modulation polarity between the input and output video signals to/from the demodulator to enable the latter to operate to the correct standard at all times.

Abstract translation: 用于自动选择具有用于解调信号的输出的中频解调器和所谓的标准选择输入引脚的视频信号的解调标准的方法和相关装置包括检测 在解调器的输出处解调信号，并将该极性与输入信号的极性相比较，将其与解调器进行比较。 在检测与解调器之间的输入和输出视频信号之间的不同调制极性时，标准选择引脚上的电压值被切换，以使其能够始终以正确的标准运行。

公开(公告)号：US5032887A

公开(公告)日：1991-07-16

申请号：US344568

申请日：1989-04-28

Applicant: Carmelo Oliveri ,  Alfonso Patti ,  Sergio Fleres

Inventor： Carmelo Oliveri ,  Alfonso Patti ,  Sergio Fleres

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74 ,  H01L29/744

CPC classification number: H01L29/66303 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/73

Abstract: A bipolar power semiconductor device, particularly a transistor, of structure formed by a matrix array of cells operating as emitter regions, comprises two separated and superposed layers of metal, one for the base and one for the emitter, separated by a layer of polyimide, as an intermediate dielectrtic.

公开(公告)号：US5031023A

公开(公告)日：1991-07-09

申请号：US548710

申请日：1990-07-06

Applicant: Bruno Murari ,  Giordano Seragnoli

Inventor： Bruno Murari ,  Giordano Seragnoli

IPC: H01L23/40

CPC classification number: H01L23/4006 ,  H01L2023/405 ,  H01L2924/0002

Abstract: A Single-In-Line molded resin package for a medium-power semiconductor device destined to receive an external heat sink mounted thereon is provided with one or more parallel open ended slots, perpendicular to the coupling face with the heat sink and open on the side of the package opposite to the side from which the pins projects.The stems of the fastening screws which may be conveniently pre-arranged on the coupling face of the heat sink are slidingly received in the respective open ended slots or notches of the various devices aligned on the printed circuit card thus simplifying the assembly operations and making them more compatible to automation.

公开(公告)号：US5028979A

公开(公告)日：1991-07-02

申请号：US488148

申请日：1990-03-05

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L29/7885

Abstract: The table cloth matrix comprises a semiconductor substrate, wherein there are contained in deep layers, under strips of field oxide, source lines and drain lines parallel to one another, areas of floating gate connecting said source lines and drain lines and control gate lines, parallel to one another and perpendicular to said source lines and drain lines, in a condition superimposed over said floating gate areas. Each source line is alternated with two drain lines separated by an insulation zone, so that each drain line is associated with a single row of matrix cells.

公开(公告)号：US5027250A

公开(公告)日：1991-06-25

申请号：US370442

申请日：1989-06-23

Applicant: Carlo Cini ,  Bruno Murari

Inventor： Carlo Cini ,  Bruno Murari

IPC: G05F1/56 ,  G05F3/18 ,  H02H9/04

CPC classification number: H02H9/046 ,  Y10T307/839

Abstract: An electronic circuit with a protection device against fluctuations in the supply battery voltage, being of a type which comprises a MOS power transistor connected between one pole of the battery and an electric load for driving said load to ground, further comprises a pair of Zener diodes connected to each other in a push-pull configuration, between said pole and the gate electrode of the power transistor.

公开(公告)号：US5013672A

公开(公告)日：1991-05-07

申请号：US259261

申请日：1988-10-18

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/033 ,  H01L21/762

CPC classification number: H01L21/033 ,  H01L21/76205 ,  H01L21/76216 ,  Y10S148/103

Abstract: The process calls for determination of the contact areas occupied by the collector, emitter and base implantations by selective removal of a layer of oxidation resistant material only from said contact areas and not from the separating zones between said areas.

公开(公告)号：US5003511A

公开(公告)日：1991-03-26

申请号：US274886

申请日：1988-11-22

Applicant: Maurizio Secol ,  Maurizio Gaibotti

Inventor： Maurizio Secol ,  Maurizio Gaibotti

IPC: G11C17/00 ,  G11C5/06 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/12 ,  G11C5/066 ,  G11C5/143 ,  G11C5/146

Abstract: Two P channel selection transistors are inserted in respective connecting circuit branches between two external pins with voltages Vcc and Vpp respectively and an internal node. A switching circuit controls said selection transistors. Circuit means are provided to hold the body bias of the selection transistors at a voltage equal to the highest voltage present from time to time at said external pins.

公开(公告)号：US4992680A

公开(公告)日：1991-02-12

申请号：US456782

申请日：1989-12-27

Applicant: Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

Inventor： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177 ,  H03K23/54

CPC classification number: H03K19/1735 ,  H03K19/17708 ,  H03K23/542

Abstract: A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.