公开(公告)号：US6130558A

公开(公告)日：2000-10-10

申请号：US104152

申请日：1998-06-23

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K19/00 ,  H03K19/096

CPC classification number: G11C7/1078 ,  G11C7/1006

Abstract: A circuit and method are described for transferring data in a semiconductor memory in synchronism with a reference clock. A data transfer circuit according to the invention includes a non-overlapping clock generator, a data output circuit, and a data input circuit. The non-overlapping clock generator generates a plurality of non-overlapping clock signals, each of which is active during a different time interval during a period of one external clock cycle. The data output circuit selects and outputs a selected one of a plurality of internal data signals in response to an active one of the non-overlapping clock signals. The data input circuit then receives the selected one of the internal data signals and outputs it to the semiconductor memory in response to the active one of the non-overlapping clock signals. By utilizing a non-overlapping clock generator to produce multiple clock pulses during a single external clock cycle, each of which triggers data transfer, data processing speed and operation rate is improved. Detrimental increase in power consumption, which normally results from an increase in the operation rate within the circuit, is reduced by removing the need for multiple input receivers.

Abstract translation: 描述了与参考时钟同步地在半导体存储器中传送数据的电路和方法。 根据本发明的数据传输电路包括非重叠时钟发生器，数据输出电路和数据输入电路。 非重叠时钟发生器产生多个不重叠的时钟信号，每个时钟信号在一个外部时钟周期的周期期间在不同时间间隔期间有效。 数据输出电路响应于非重叠时钟信号中的有效一个，选择并输出多个内部数据信号中的所选择的一个。 然后，数据输入电路接收所选择的一个内部数据信号，并响应于非重叠时钟信号中的有效一个而将其输出到半导体存储器。 通过利用不重叠的时钟发生器在单个外部时钟周期期间产生多个时钟脉冲，其中每个时钟脉冲触发数据传输，数据处理速度和操作速率得到改善。 通过消除对多个输入接收机的需要，减少了通常由电路内的操作速率的增加导致的功耗的不利增加。

公开(公告)号：US5920511A

公开(公告)日：1999-07-06

申请号：US996192

申请日：1997-12-22

Applicant: Sang-bo Lee ,  Jung-bae Lee

Inventor： Sang-bo Lee ,  Jung-bae Lee

IPC: G11C7/10 ,  G11C16/04

CPC classification number: G11C7/1066 ,  G11C7/1072 ,  G11C7/1078

Abstract: A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

Abstract translation: 用于半导体存储器件的数据输入电路使用回波时钟发生器来减少时钟周期时间。 回波时钟在数据存储器中传输，从而减少时钟偏移的影响，并提高整体设备的运行速度。 该电路特别适用于双倍数据速率同步DRAM（DDR-SDRAM）电路。

公开(公告)号：US09575923B2

公开(公告)日：2017-02-21

申请号：US14818586

申请日：2015-08-05

Applicant: Young Chul Cho ,  Jung Bae Lee ,  Jung Hwan Choi

Inventor： Young Chul Cho ,  Jung Bae Lee ,  Jung Hwan Choi

IPC: H03K19/003 ,  G06F13/42 ,  H03K19/00 ,  G05F1/625

CPC classification number: G06F13/16 ,  G05F1/625 ,  G06F1/3287 ,  G06F13/4068 ,  G06F13/4221 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract translation: 操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。 另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。 另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

公开(公告)号：US08891324B2

公开(公告)日：2014-11-18

申请号：US13915338

申请日：2013-06-11

Applicant: Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

Inventor： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  H01L27/02 ,  H01L27/105 ,  G11C7/18 ,  G11C11/4091 ,  H01L27/108

CPC classification number: G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract translation: 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08736296B2

公开(公告)日：2014-05-27

申请号：US13163884

申请日：2011-06-20

Applicant: Hoe ju Chung ,  Jung bae Lee ,  Hoon Lee

Inventor： Hoe ju Chung ,  Jung bae Lee ,  Hoon Lee

IPC: G01R31/26 ,  H01L21/66 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract translation: 本发明提供一种包括堆叠的多个装置和相关方法的装置。 该装置包括堆叠的多个装置，包括主装置和至少一个次装置; 多个段，每个段与堆叠的多个设备中的一个相关联; 以及穿过堆叠的多个装置的多个N个垂直连接路径。 该装置还包括由多个N个垂直连接路径构成的多个M个垂直信号路径，其中M小于N，并且多个M个垂直信号路径中的至少一个是被自适应地由 主设备使用来自多个N个垂直连接路径中的至少两个中的每一个的至少一个段。

公开(公告)号：US20130272047A1

公开(公告)日：2013-10-17

申请号：US13915338

申请日：2013-06-11

Applicant: Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

Inventor： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract translation: 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08473694B2

公开(公告)日：2013-06-25

申请号：US12885728

申请日：2010-09-20

Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

IPC: G06F12/00

CPC classification number: G11C29/08 ,  G11C11/401

Abstract: A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.

Abstract translation: 存储器装置包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元，将存储器块分成至少第一组和第二组，并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元，并且第二组中的每个存储器块都不包括不合格存储器单元。

公开(公告)号：US20120188834A1

公开(公告)日：2012-07-26

申请号：US13441713

申请日：2012-04-06

Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US08120980B2

公开(公告)日：2012-02-21

申请号：US12686561

申请日：2010-01-13

Applicant: Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

Inventor： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

IPC: G11C7/02

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4091

Abstract: A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

Abstract translation: 半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

公开(公告)号：US20120039404A1

公开(公告)日：2012-02-16

申请号：US13280456

申请日：2011-10-25

Applicant: Hoe-ju CHUNG ,  Jung-bae LEE

Inventor： Hoe-ju CHUNG ,  Jung-bae LEE

IPC: H04L7/00 ,  G06F12/00 ,  H04L27/06

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。